True 3D needs EDA and 300mm

by Ed Korczynski, Senior Technical Editor, Solid State Technology

System-level considerations of 3D ICs were presented by Tom Gregorich, VP of Qualcomm, in a session discussing the “Economic implications of 3D” at the ConFab in Las Vegas. He reminded the audience that end-users of portable electronics products — such as cellphones and PDA — expect reliable functionality regardless of dropping, kicking, or washing the device. Delivering ever greater functionality in essentially the same robust package is a mandate for innovative concepts such as 3D.

Since the launch of the Apple iPhone in 2007, it seems that nearly any portable electronic function that had been performed by a unique device can now be integrated into a cell phone. Playing music and video files, searching maps and directions, gaming, photography, and even traditional computing functions are all available on a phone today. Consequently, in addition to the essential cell phone baseband and RF functions, handsets now include a wide variety of inputs and outputs.

However, cost of integration remains an issue. We are past the early years of the cell phone business when cost was the only deciding factor in handset purchases, and since the iPhone’s debut the drive to ever-smaller devices is over. Now, consumers expect low-cost, modest-size, and amazing performance from handsets. Microprocessor packages have evolved from 0.5mm QFP to ≤1.0mm BGA to 0.4-0.5mm chip-scale packages to pack in more performance. In addition to conventional flip-chip, this year should see the first volume use of package-on-package and package-in-package flip-chip technology.

Through-silicon-vias (TSV) certainly result in the smallest packages, the best electrical performance, and potentially greater freedom for manufacturers to customize functionality for different end-markets. However, Qualcomm doesn’t see that TSV and 3D wafer fab technology are ready for production. If the technology were ready today, it’s possible that integration costs could be reduced enough to complete with simple stacking using wire-bonders.

True 3D architecture requires a revolution in design, but should provide for the use of new super-wide busses, allow more flexibility in partitioning, and eliminate some matching circuitry. In addition, a 3D design should reduce the overall power consumption through efficiency gains in system functions such as matching and memory refreshing.

Despite all of the potential for true 3D design, Gregorich characterized the current state of the art as a “train-wreck.” Challenges yet unmet include 300mm wafer processing tools based on standards for interfaces and process flows, development of 3D design tools, achievement of ≥95% assembly yield, and thermal management. To be sure, there are many teams around the world working to solve these issues, but we still have a way to go.

The first-order TSV cost model used by Qualcomm includes factors for via formation, circuit area lost, and stacking processes. TSV formation costs include deep silicon etching, dielectric isolation, and metal filling. Some silicon 2D circuit area must be lost to allow for TSV formation, and so dice must be larger and costlier. Through-silicon stacking costs include wafer thinning and bonding too.

Despite the known challenges, Qualcomm is committed to the idea of TSV in 3D packages sometime in the future. A roadmap for TSV should be established to standardize global development, including when to target deployment of via-first or via-last TSV, via diameter and pitch, and die aspect ratio by node. In addition, pre-competitive alliances could work on standardizing interfacial metallurgies, and process flows that may need carrier/”handle” wafers for volume production. — E.K.

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