C. Mark Melliar-Smith, S.V. Sreenivasan, Molecular Imprints Inc., Austin, TX, USA
Over the past 40 years, the ability to make smaller features with improved optical lithography has been the basis for Moore’s Law and the incredible advances in CMOS technology. However, continued extension to 50nm features has become increasingly difficult and expensive, placing Moore’s Law in some degree of jeopardy over the next decade. Sub-wavelength imaging has become common in the industry, but this has come at a significant price in terms of cost, complexity and design rule restrictions. The industry has been aware of the challenges of sub-wavelength imaging for many years and the dramatic move to 13nm—referred to as Extreme Ultra Violet (EUV)—has been the subject of intense effort over the past decade. However, the technical challenges associated with using X-ray wavelengths (not withstanding the EUV name), which are not transmitted by any materials including air, have proved to be almost insurmountable.
Step and flash imprint lithography
Recently a new technology, called Step and Flash Imprint Lithography (S-FIL), has gained attention as an alternative to EUV for CMOS lithography . This process, shown schematically in Fig. 1, uses an electron-beam generated imprint mask to pattern a low viscosity liquid, which is then solidified by a flash of broadband UV light. Since the resolution of the patterns is controlled solely by the imprint mask, the process does not suffer from any of the wavelength imaging issues that have plagued optical lithography, with features as small as 5nm being demonstrated .
1. Schematic of step and flash imprint lithography process.
Recently published results [3-7] by companies such as Samsung, IBM, and Hewlett-Packard have also demonstrated the lithographic capability of the technology. Additionally, Toshiba conducted a comprehensive technology evaluation of S-FIL technology at one of its facilities to help determine how to approach the lithography of their next-generation device architectures. Figure 2  gives an example of the data that Toshiba presented in this evaluation, illustrating resolution down to 18nm with excellent line-width roughness (<2nm) and overlay (mean + 3σ) approaching 10nm. Resolution and line-width roughness are areas where the S-FIL process leads in performance compared to competitive sub-32nm lithographic alternatives, while the overlay performance demonstrated lends confidence that S-FIL should be capable in time of meeting requirements for manufacturing
2. Imprint results from Toshiba presented at the SPIE Advanced Lithography Conference in February 2008, showing both 18nm minimum feature size and overlay approaching 10nm.
Toshiba, like other companies publishing on S-FIL lithography, leads the industry roadmap by as much as three years in order to meet the memory density requirements demanded by their customers. Hence the growing interest in imprint lithography as a cost-effective route to higher-resolution lithography.
While high-resolution patterns and tight overlay demonstrate the feasibility of S-FIL, lithography success requires that S-FIL withstand the rigors of a CMOS fab/process in production. This presents a number of challenges for a new technology, of which three are especially critical:
- Cost-of-ownership—does the new technology offer a significant advantage;
- Compatibility with existing CMOS processes; and
- Extendibility—can the technology be used for more than 1 or 2 nodes.
Cost-of -ownership (CoO)
The rapid increase in the cost of CMOS lithography has placed considerable pressure on CoO. While throughput and the capital cost of the tool are major contributors to lithography CoO, they are now being rivaled by the additional cost of process complexity for 193nm double patterning, and by the cost of masks for both double patterning and EUV. S-FIL can offer significant cost advantages in all of these segments—throughput, capital, process complexity and mask costs. CoO estimates for 193nm optical, EUV and S-FIL are shown in Fig. 3.
3. Relative CoO calculations for various options at 22nm half-pitch relative to single exposure 193nm immersion at 45nm.
Figure 3 shows the rapid increase in 193nm lithography CoO from patterning for 45nm, versus that required for 22nm (double spacer patterning). Estimates are shown for EUV assuming a realistic 50wph throughput (given the challenges in both sources and resists) and an estimate for a 4-head imprint cluster tool, running at 80wph.
The absence of expensive lenses, light sources and vacuum chambers reduces the cost of S-FIL patterning tools by as much as a factor of 10 relative to photon-based equipment. The combination of low tool cost and cluster tooling significantly reduces the equipment-related component of CoO for S-FIL relative to 193nm double patterning and EUV.
S-FIL imprint masks use a 1x technology as opposed to 4× reduction masks used in optical lithography systems. However, the S-FIL process is completely free of design rule restrictions, whereas the 4× masks used in optical lithography make use of sub-resolution OPC features down to 1.5×—making 1× masks a far less daunting prospect than once viewed. In addition, 1× masks can be replicated to reduce their cost. A single master mask is made using standard mask production technology (6025 glass, e-beam write, etch, inspection). This “mother” mask can then be used to print additional “daughter” masks, which are used to equip multiple imprint tools in a manufacturing line. In contrast, optical lithography technologies must use master masks for each exposure tool.
The combined advantages of low capital cost, single step lithography and replicated masks makes the total CoO for S-FIL technology much lower than optical and EUV lithography alternatives. In fact, as shown in Fig. 3, imprint lithography even has the potential to reduce lithography cost at 22nm to below that incurred with a single exposure optical lithography process at 45nm.
Demonstrating low defectivity is a crucial requirement for any new process technology. Dramatic improvements in the defect levels for S-FIL have been demonstrated over the past four years, as shown in Fig. 4.. These results, averaging approximately an order of magnitude improvement each year, closely parallel the learning curve for immersion lithography, but tracking about two years behind. This is an important comparison, since immersion is the most recent major lithography change and is somewhat similar to S-FIL in terms of defectivity, since both must deal with the issue of patterning through a liquid.
4. Defect density data for S-FIL imprint lithography, compared to immersion lithography.
Contributors to defectivity in S-FIL include mask defects, micro-bubbles, particles, and wafer and material contamination, all of which occur in immersion lithography and have been addressed in the past—resulting in defect learning from which S-FIL has benefited. Specific to S-FIL are defects related to preferential adhesion of the exposed resist to the imprint mask, which will leave a void in the pattern. However, such defect mechanisms have been virtually eliminated by optimizing the mechanical properties of the resist and the release performance from the imprint mask.
Based on the data and improvements seen to date, S-FIL appears on track to reach defect levels required for CMOS manufacturing. However, the final improvements necessary to achieve that goal will be demonstrated by tools installed in CMOS fabs.
Compatibility with existing CMOS processes
Any new technology must be compatible with the existing processes upstream and downstream in the process flow. CMOS device fabrication and process integration is much too complex an operation to allow wholesale changes to accommodate any new technology, no matter how attractive. S-FIL meets this compatibility requirement. It is a literal “drop-in” complement for existing optical lithography.
The patterned imprint resist possesses similar aspect ratios and relative etch rates as today’s 193nm resists and the wafers require no special pre- or post-processing techniques beyond those already available in existing fabs. S-FIL systems can be mix-and-matched with existing 193nm scanners, with field sizes up to 26mm×32mm. In addition, the imprint masks are manufactured by the same suppliers that produce today’s photomasks using the same processes, but with the additional advantage of no OPC or mask error enhancement factor (MEEF) issues.
Evidence of this compatibility was demonstrated in 2007 by IBM, in collaboration with the Advanced Technology Development Facility (ATDF), KLA-Tencor, Applied Materials, Hoya and Dai Nippon Printing. In work directed at addressing multiplexing issues associated with high-density cross-point-style non-volatile memory, electrically functional 30nm FinFET devices were produced . S-FIL was used to define the critical fin features in a seven mask process that required imprint lithography to mix-and-match overlay to conventional 193nm optical lithography, to ∼20nm. The imprinted features were plasma-etch transferred into an oxide hard mask to produce features exhibiting very good line-width roughness (<2nm) and CD uniformity. Images of the resulting pattern-transferred and CMOS-processed features are shown in Fig. 5.
5. SEM image of SFIL-defined silicon Fins and TEM image of processed Fins ready for ion implantation.
The low cost and high performance of S-FIL has created other nanofabrication applications, several of which will likely precede the technology introduction into CMOS, providing significant manufacturing learning experience.
The hard disk drive industry, for example, is quickly taking advantage of the cost/performance characteristics of S-FIL. Like CMOS, this industry needs to use smaller memory bits to enhance its storage capacity each year, with hard disk companies targeting an areal density of 1 terabit/in² around 2010 with a continued 50% density compound annual growth rate through the next decade. Below about 25nm, the bits have to be patterned and etched into the disk media to prevent thermal instability while improving the signal to noise. At the same time, the industry cost structure dictates that the costs of patterning (litho, etch, planarization, etc) add no more than ∼$2 for each double-sided disk. Further, to meet the volume demands at a low CoO, lithography tools must be capable of producing >600 double-sided disks/hr. These demands are daunting: 10 trillion sub-25nm pillars printed on both sides of the disk at 600 disks/hr. Only S-FIL imprint lithography has the capability to meet these requirements.
Because S-FIL offers the potential to produce high volumes of precision nano-dimensioned features and parts at very low cost, a host of potential applications in biotechnology, optics, and clean/green technologies await on the horizon. For example, by replacing traditional incandescent bulbs by 2020, solid state lighting is expected to save 50 tera watt hours (TWh) of power and 60 million tons of carbon per year. The keys to accomplishing this are increasing the brightness and efficiency of light emitting diodes (LEDs), which imprint lithography can enable by printing a nano-scale photonic crystal on the surface of the LED.
In less than seven years, imprint lithography has emerged as a leading candidate to extend and complement optical lithography in semiconductor memory applications cost-effectively. It offers layout designers the opportunity to return to the days before “design for manufacturing” (DFM), eliminating OPC, phase shift mask (PSM), and the massive computer farms supporting computational lithography. It offers 22nm half-pitch resolution while retaining 193nm lithography CoO, along with single exposure and single etch, while eliminating costly resist tracks. And it can be comfortably added to existing optical lithography cells in a mix-and-match environment.
Step and Flash and S-FIL are registered trademarks of Molecular Imprints Inc.
1. C.M. Melliar-Smith, “Lithography Beyond 32nm: A Role for Imprint?,” Proc. of SPIE Advanced Lithography, Vol. 6517, xxi (2007).
2. F. Hua et al., Nano Letters, 4, 2467 (2004).
3. I. Yoneda et al., “Study of Nanoimprint Lithography for Applications Toward 22nm Node CMOS Devices,” Proc. of SPIE Advanced Lithography, Feb. 2008, Vol. 6921, 6921-03.
4. Kim, K.T. et al., “Full-field Imprinting of Sub-40nm Patterns,” Proc. of SPIE Advanced Lithography, Feb. 2008, Vol. 6921, 6921-05.
5. F. Houle et al., “Chemical and Mechanical Properties of UV-cured Nanoimprint Resists,” Proc. of SPIE Advanced Lithography, February 2008, Vol. 6921, 6921-10.
6. W. Tong et al., “Hybrid Circuit of CMOS and Crossbar Nanowires by Nanoimprint: Semiconductor Nanowire Interconnects (SNIC),” Proc. of SPIE Advanced Lithography, February 2008, Vol. 6921, 6921-08.
7. M. Hart, “Step-and-Flash Imprint Lithography for Storage-Class Memory,” Intl. Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), June 2007 and IEEE Lithography Workshop, December 2007.
8. I. Yoneda, op.cit.
9. I. McMackin et al., “High-resolution Defect Inspection of Step and Flash Imprint Lithography for the 32nm Node and Beyond,” Proc. of SPIE Advanced Lithography, February 2008, Vol. 6921, 6921-86.
10. M. Hart, op.cit.
C. Mark Melliar-Smith received his BS and PhD in chemistry from Southampton University (England) and an MBA from Rockhurst College in Kansas City, and is CEO at Molecular Imprints Inc., 1807 West Braker Lane, Building C-100, Austin TX 78758-3605 USA; ph.: 1-512-339-7760; e-mail mark (at) molecularimprints.com.
S.V. Sreenivasan received his B. Engr in mechanical engineering from the National Institute of Technology, Trichy (India), and his PhD in mechanical engineering from Ohio State U. He is a co-founder and CTO of Molecular Imprints Inc. He is also the Thornton Centennial Faculty Fellow in engineering at the University of Texas at Austin.