Report from the VLSI Symposium: Planar CMOS to 22nm, but no more

by John O. Borland, Editorial Advisor, Solid State Technology

July 1, 2008 – This year’s VLSI Symposium meeting (June 16-19, Waikiki, Hawaii) highlighted 45nm to 16nm CMOS technology. Overall, most agreed that planar CMOS is extendable to 22nm node but unlikely beyond that — e.g., by the 16nm node SRAMs will need FinFET or a trigate-like design. These can be fabricated in bulk wafers rather than SOI wafers, as first reported by Toshiba in 2006 — and now by many others including Intel and Hynix, revealed during this year’s symposium.

On Monday 6/16, the day before the Symposium’s official opening, a short course highlighted CMOS logic technology challenges for the 32nm-22nm transition. Matthew Colburn of IBM’s research division stated that straight scaling of designs will not work at 22nm, and that litho-design co-optimization and double patterning techniques are key tools in the extension of optical lithography. Jack Kavalieros of Intel Components Research noted that we have moved from classical scaling to power-efficient scaling that involves new processes, new materials, novel device structures, and co-optimization with the design community. Showing the tri-gate architecture, he explained that tri-gate/FinFETs can be fabricated on either bulk or SOI wafers — and that most of Intel’s recent work is with bulk wafers and not SOI (see Fig.1). He also showed results on III-V and Ge quantum wells on silicon, with GaAs mobility >8× that of Si while InSb is >50×. He also talked about steep sub-threshold swing devices for electronics with extremely low power.

Fig.1: Intel’s FinFET on a bulk wafer. (Source: Intel)

32nm and 22nm BEOL will be an evolution extension of previous interconnect schemes, with dual damascene Cu/low-k integration continued with slow introduction of new materials and processes, said Hans-Joachim Barth of Infineon Technologies. Major reliability challenges are electromigration, stress migration, dielectric reliability (TDDB), and chip-package interaction, as well as design-for-manufacturing (variation tolerant, RC and cross-talk optimized wiring) for good production yield. Low-k is needed; he noted, however, issues include thermo-mechanical and film stress and adhesion, as well as tensile stress, which leads to cracks. Infineon’s efforts will try to stay with PVD for high-purity barrier and seed layers, he noted, because with CVD, purity is not as good. One problem with Cu is increased resistivity for narrow lines due to Cu grain boundaries. Beyond Cu/low-k will be optimized wiring layout and 3D-chip stacking in the future, he said.

A talk on embedded SRAM given by Yong Shik Kim of Samsung’s device technology group described challenges for 22nm, including reducing device variations and vertical cells (FinFET or 3D cell). He showed Toshiba’s results from 2006 on embedded bulk wafer SRAM FinFET structures (see Fig. 2).

Fig. 2: Planar CMOS with embedded bulk FinFET for SRAM. (Source: H. Kawasaki, et al., VLSI Symp., 2006, paper #9.2, p. 86)

In other Monday presentations, Phil Dahl of Freescale Semiconductor showed that combining system-on-chip (SoC) with system-in-package (SiP) adds value for the end customer with miniaturization (more Moore) and diversification (more than Moore). And Hisao Yoshimura of Toshiba’s advanced logic technology department reviewed DFM strategy for random defects, systematic defects and parametric variability, pointing out their relation to lithography and process such as optical proximity correction (OPC) and pattern correction/density control.

Notable papers on Tuesday included the IBM alliance reporting on the performance advantages of FinFET at 22nm over planar to be 17%. Toshiba showed a single S/D structure using DDS (dopant segregated schottky) using the “snow plowing” effects of arsenic dopant during silicidation. Selete discussed using Al doping for pMOS high-k and La, Mg, Y, or Sc for nMOS high-k.

In a plenary talk entitled “Has the sun finally risen on photovoltaics?” Mark Pinto of Applied Materials noted that in 2008 PV will use more silicon than the IC industry. Equipment throughput is about >1000 wafers/hr with 13%-22% efficiency for low-cost silicon and up to 40% with GaAs for aerospace applications. Substrates are glass or <150μm silicon wafers for flexible material.

The Wednesday highlight session belonged to Hynix, which showed a 44nm DRAM built with a saddle-Fin structure, a combination of RCAT (2D single gate) and a bulk FinFET (3D triple gate). Meanwhile, IBM and alliance partners Freescale, CSM, Infineon and Samsung reported their 32nm node Hi-k/MG (single metal/gate first) for low cost low power — using bulk CMOS and not SOI! For low cost no eSiGe is used and a capping layer is used with the high-k. SEMATECH reported work involving p-channel on SiGe with HK+MG. They used nitridation to suppress interfacial layer growth, and found plasma nitridation was better than thermal nitridation. Without surface nitridation, gate leakage degraded by 10&times.

Intel reported on its work on floating body cell (FBC) memory with HK+MG, on thin silicon (22nm) and thin buried-oxide (10nm) SOI wafers for the 16nm node and beyond.

Intel also disclosed more details about its 45nm node HK+MG strain-enhanced transistors (see Fig. 3), claiming only a 4% increase in wafer costs. Similar to what Sony reported during this year’s Symposium, Intel also said that the metal gate last improves strain-Si. For 65nm nMOS they used tensile CVD liners and SMT using implant and anneal; at 45nm, Intel moved to tensile stress trench contact. For the pMOS they increased Ge content up to 30% and moved the eSiGe closer to the gate edge. It was found that a dummy gate in which the removal of the sacrificial polysilicon gate layer (see Fig. 4) allows more compressive strain to be created in the channel region — because of compressive strain from SiGe features on either side — improved the pMOS by 51% to 1.07mA/μm, making it almost as good as the nMOS (1.36mA/μm), which was only 12% improved (see Fig. 5).

Fig.3: X-TEM showing nMOS with tensile stress trench contact and pMOS with eSiGe. (Source: Intel)

Fig.4: Stress contours in the pMOS before and after dummy gate removal. (Source: Intel)

Fig.5: Ion-Ioff improvement of 12% for nMOS and 51% for pMOS transistors from 65nm to 45nm node. (Source: Intel)

Elsewhere, Sony reported that with eSiGe the replacement gate process improves the compressive channel strain. And Selete discussed work on the concept of adding a spike-like anneal after a flash anneal step to recover the damage caused to HK+MG such as BTI lifetime and mobility. They call this “flexibly-shaped-pulse” flash lamp annealing.

Thursday ushered a collection of papers involving implant and doping schemes. Renesas reported the smallest Vt variation by eliminating the halo implant, switching from poly to FUSI gate metal, and using thin BOX (<10nm) SOI. IBM said the best method to dope eSiC stressors is with P either in-situ or by implantation, noting that a P implant degrades carbon substitution. TI reported on 45nm node stressor integration to prevent dislocation, showing that a low (<0.1%) C doping to eSiGe reduced dislocation and N2 implant was used to pin dislocations. IMEC discussed its 32nm node laser annealed junctions from a device performance and manufacturability perspective, showing reducing device junction leakage but engineering the location of end-of-range implant damage. And Fujitsu said high-temperature millisecond annealing degrades short channel effect, and that a tilt-and-twist extension implant improved performance by 7% due to gate overlap control.

The U. of Singapore had a paper on eSiGeSn and eSiC using Sn and C implantation with laser melt annealing. With 7% Sn they saw 35% pMOS Idsat in (100) silicon and 71% in (110), whereas with a 5E15 dose C implant they achieved 1.5% substitution and increased nMOS Idsat by 19%. — J.O.B.

John Borland is founder of J.O.B. Technologies, and a member of SST’s Editorial Advisory Board.


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