SEMICON West Packaging Summit Address Path to TSV Adoption

(July 15, 2008) SAN FRANCISCO &#151 In a panel discussion hosted by Bill Bottoms, CEO of Nanonexus, and Jan Vardaman, TechSearch International, Industry experts from IBM, Intel, R3Logic, TSMC and Amkor emphasized a growing need for TSV adoption, what the drivers will be, how they will be used beyond being a replacement for electronic wiring, and what needs to happen to achieve this by established timelines.

Before opening the floor to questions, each panelist offered a brief summary of their company’s perspective on the topic. John Knickerbocker, IBM distinguished engineer, manager of system-on-package, 3D integration, IBM Research Division, Thomas J Watson Research Center, talked about research IBM is conducting around TSV application and adoption. He said TSV provides the architecture for low cost, performance scaling and power savings for computers and servers. It also allows for more integrated functionality in cell phones and other portable electronics. “At IBM we’re trying to drive a database and establish ground rules,” he noted.

Bob Sankman, package pathfinding manager, assembly test technology development, Intel Corp. offered Intel’s perspective on advantages of 3D such as higher performance due to shorter wire lengths. He said shorter wire connection lengths allow for decreased signal power, shorter delay times, smaller form factors and the ability to integrate heterogeneous devices, for which system-on-chip SoC isn’t practical. With it, you can mix and match dram, CMOS, optical devices, etc. “TSV will play some role in the future, it’s just a matter of finding the right spot for it,” said Sankman.

A comment from the floor emphasized the need to distinguish between 3D advanced packaging and 3D IC 3D packaging can have heterogeneous integration, with 3D IC, need to start with silicon design.

The issue of developing 3D EDA tools needed for TSV adoption was addressed by Lisa MacIlrath, Ph.D., president, R3Logic, Inc. “It (3D chip and package design) used to be easier, and could be accomplished with existing tools. That’s still possible as long as only dealing with a few layers.” In the early days of 3D, designs could be done by hand. The critical question is whether the lack of design tools will slow the adoption of 3D. Although some true 3D commercial tools exist, MacIlrath said that there is a need to accelerate the development of digital 3D IC design tools. She also said there is a need to integrate existing 2D flows with 3D. “It’s something that needs to be done right now.” She stressed.

Clinton Chao, Ph.D. deputy director, backend technology development division, TSMC, explained the difference between via-last TSV processes, and via-first. Via last is a post IC process, and via-first is an integral part of the IC wafer process, and will soon achieve smaller geometries than the alternative.Robert Darveaux, Sr, VP, packaging and research development, Amkor Technology, expanded on the via-first and last processe, explaining that there are two options for both. Via-first and what he called via-early are both done in a front-end fab environment, while via-last on the wafer front side can be performed either in the fab or as an outsourced semiconductor assembly and test (OSAT) process. Via-last on the back-side is strictly an OSAT process.

The question and answer portion of the summit sparked some interesting discussion. Bottoms posed the possibility that although replacing electrical wiring is a known application, early adoption may be something else. A flurry of suggestions followed. Sankman suggested TSV could allow for an interposer between the die and package to allow for a redistribution path. “There are a good deal of creative areas to explore TSVs, but the most appealing is for short wiring density approach,” he said.

Chao suggested that we might see it in LED packaging in near future. MacIlrath maintained that a single driver, such as the multicore processor, is required to get the technology off the ground, but that many other applications will follow. Among those is 3D imaging, in which TSV will allow for processing to be put behind each pixel.

Bottoms suggested another application could be for thermal management. MacIlrath noted that that a study done at the University of Minnesota has done research for thermally-aware TSV placement and routing, and has achieved good results with benchmark cases for allieviating thermal stress.

Application will be driven by need, noted Knickerbocker. First applications have been discussed and include image sensors, memory stacks, multicore processors to memory cache, and high density needs.

When an attendee queried the panel on their opinion of heterogeneous integration needs as a driver for TSV the question was met with no response. “The answer is they’re keeping their thoughts to themselves,” quipped Bottoms. “We discussed the impact of heterogenous integration and decided it was too early to address it. We must have been correct.”


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