WCJTG speakers summarize 32nm USJ progress

Presenters at the AVS Northern California Chapter of the West Coast Junction Technology Group Meeting (WCJTG), told SST‘s senior technical editor Debra Vogler about their research and their presentations.


Susan Felch, principal member of the technical staff, Spansion: “For 32nm USJs, we’re going to need to go to millisecond anneal (MSA)-only, however there are various integration issues/ compatibilities that need to be dealt with that all have their process windows. For example, we need to be compatible with the HK+MG stack if embedded Si-Ge is going to be used — that places limitations on how high the temperature can go. On the other hand, in terms of getting the activation that’s required and the defect annihilation so that we get low leakage — that requires going to higher temperature. So for different customers’ integration schemes and device structure, they’re going to have to find a proper process window where they can get all of the benefits and compatibilities with that MSA.”

Jeff Hebb, VP of product marketing, Ultratech: “We have a long wavelength laser [in Ultratech’s LSA system] and we come in at a certain angle and polarization that makes the wafer very uniform to the laser. That allows us to do these processes without using any coatings or absorber layers. And also, with the LSA system, you can vary the dwell time easily and go to low dwell times. As far as extending LSA to 32nm and beyond — we looked at stress techniques, especially SiGe: going to the low dwell time is critical so you don’t end up with excessive wafer warpage or stress defects. And we also looked at HK+MG and showed how pattern independence still holds true — it still works for HK+MG integration schemes. And in a recent IBM paper (VLSI Symposium 2008), it was shown that LSA didn’t have negative effects. In a couple of papers from Freescale Semiconductor — they used LSA to do a high-k annealing to improve the properties of a dielectric. And lastly — extending beyond 32nm with alternate device structures — we’ve already demonstrated that we have good results with ultrathin SOI — so we think there shouldn’t be any issues with FinFETs. We think LSA is easily extendible to 32nm.”

Alex Salnik, principal scientist, KLA-Tencor: [Summarizing new developments on projects being done jointly with IMEC] “We have two on-going projects with IMEC. One is related to the correlation of the micro-uniformity maps to the actual device performance. IMEC has the capability of doing that — they can obtain the maps and follow the micro non-uniformities and correlate them if possible. That will provide the important early-stage detection of such defects. The second project with IMEC is related to carrier depth profiling as a potential replacement for SIMS. We started with a simple, diffuse, box-like profile, seeing if we can reconstruct the profile using our technology. We’ve already been working on this for one year, we expect that soon, we’ll be ready to show whether it’s really a solution.”

John Borland, founder, J.O.B. Technologies, member of SST‘s Editorial Advisory Board: “I talked abut reducing device variability and process variability. The key is having rapid process optimization metrology that allows you to connect any variation in both implant and annealing so that the combination will give you good device uniformity [see “32nm node USJ formation using rapid process optimization metrology”, SST July 2008, pp 38-47). Additionally, just using Rs and Xj can be very misleading when there’s no diffusion because the pre-amorphization (PAI) to improve activation will lead to leakage, and therefore EOR damage and poor quality junctions. So that’s why measuring junction quality is very important, otherwise you optimize the wrong process.” — D.V.


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