Bright future for LSA at 32nm and beyond

by Debra Vogler, Senior Technical Editor, Solid State Technology

August 28, 2008 – USJ formation at 32nm was the focus of the West Coast Junction Technology Group’s meeting on the final morning of this year’s SEMICON West. But many presenters also discussed what lies ahead at the 22nm node. Ultratech’s Jeff Hebb, VP of product marketing, and chairman/president/CEO Art Zafiropoulo provided additional insight to SST about the company’s WCJTG talk on laser spike annealing.

The basic theory of LSA operation is the use of a long-wavelength, p-polarized “line beam” incident on a wafer at Brewster’s angle (to minimize pattern effects). The wafer is scanned under the beam — dwell time determined by the stage speed — and real-time peak temperature measurement is done with a feedback loop to the laser. “We come in at a certain angle and polarization that makes the wafer very uniform to the laser,” noted Hebb. “That allows us to do these processes without using any coatings or absorber layers, and with the LSA system, you can vary the dwell time easily and go to low dwell times.”

Pattern effects using LSA have been debated for some time. Hebb presented data illustrating the suppression of pattern effects using LSA (see Figs. 1-2), and how P-polarization and the Brewster angle make cross-die absorptivity uniform to ~1%.

Fig. 1: Suppression of pattern effects using LSA. The long wavelength (10.6μm) is much greater than the length scale of devices and films (100nm). (Source: Ultratech, WCJTG)
Click here for full-size image

Fig. 2: Measured reflectance of real die confirm suppression of pattern effects for LSA, enabling higher peak temperatures and increased device gain. (Source: Ultratech, WCJTG)
Click here for full-size image

As far as extending LSA to 32nm and beyond, the company looked at a number of options including high-k/metal gate (HK+MG), FinFETs, and stress techniques. For example, with stress techniques (SiGe in particular), “going to the low dwell time is critical so you don’t end up with excessive wafer warpage or stress defects,” said Hebb. “And we also looked at HK+MG and showed how pattern independence holds true — it still works for HK+MG integration schemes.” He added that an IBM paper presented at this year’s VLSI Symposium showed that LSA didn’t have negative effects (see Fig. 3).

Of particular interest in Fig. 3 is the notation that the data refers to IBM’s gate first process, an approach Zafiropoulo said was “very extendible.” He also believes that, although Intel has proven it can make a gate-last approach work, it will be “extremely difficult, if not close to impossible” for other chipmakers to make gate-last a production technology. “We think IBM’s approach of gate-first is probably the way the world should go — and will go,” he said.

Fig. 3: 32nm low-power transistor with high-k/metal gate (Hf-based high-k/single-metal gate-first process) shows LSA is compatible with HK+MG process at 32nm. LSA is used for USJ with no negative impact and only <3% total added cost. (Source: IBM Alliance, VLSI Symposium 2008)

Also referenced by Hebb at the WCJTG meeting were recent papers by Freescale Semiconductor in which LSA was used to do a high-k annealing to improve the properties of a dielectric. Extending beyond 32nm with alternate device structures, Hebb said that good results were already demonstrated with ultrathin SOI, “so we think there shouldn’t be any issues with FinFETs. We think LSA is easily extendible to 32nm.”

The work Hebb presented at the WTJCG meeting was entirely focused on sub-melt LSA — i.e., the temperature is kept below the melting point of silicon — and this technology is likely going to be used all the way down to 22nm. However, according to Zafiropoulo, there may come a time when the industry will need an LSA process that occurs at a higher temperature, as high as the melting point of silicon. “We have the melt technology running in our alpha systems in our lab today,” he said, noting that a few customers have used that system. “Based on what we have been told, we think melt technology will be useful below 22nm.” As an aside, Zafiropoulo told SST that the company delivered a production system for melt-LSA to a US government agency back in 1996 — and even though a system implementing melt technology today would be different, he maintains that the company understands that technology very well should it ever be needed.

Regarding the market outlook for LSA, Zafiropoulo told SST that usage at the 65nm node is growing, with the company having penetrated 16 of the top 18 companies in the logic sector, many of which have moved into production this year. And the company is seeing an even larger transition from development to production at 45nm; he anticipates that in 2009 the company will see a sharper increase in 45nm orders. — D.V.


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