Part 1: Embedded Actives
By Swapan K. Bhattacharya, Chad Patterson, and John Papapolymerou, Georgia Institute of Technology
Miniaturization with increased functionality at reduced cost has historically been the key driver for the evolution of electronics products. Size reduction was confined to lateral dimensions until real estate in the Z-direction became severely compromised. Since then, thin has become the buzz word encompassing die, dielectric, passives, and ultimately resulting in thin packages. This series of articles will overview trends from thick to thin packages with embedded RF passive and active components within a flexible microwave organic substrate that can perform at frequencies in the range 2-110 GHz.
Traditionally, mm-wave circuits are built on high-cost alumina or low temperature co-fired ceramic (LTCC) substrates that make inclusion of active chips or devices challenging and more expensive due to high temperature processing. Liquid crystal polymer (LCP) provides a promising sweet spot for low-temperature and low-cost-large-format processing on an organic platform, maintaining superior RF performance in the mm-wave range.
The semiconductor industry is faced with tremendous growth in functionality, increased speed, and performance at reduced cost and real estate. For size reduction, the likely answer lies with embedded passives, actives, and discrete components. Embedding IC within the core is not new, in fact, the concept dates back to the work of Gene Weiner at MIT Lincoln Laboratory in 1950. The team placed devices within resin and routed interconnections by mechanical drilling.1 Two decades later, Honeywell showed paths toward embedding IC in smart cards. However, the ice breaking work is credited to GE, which in the early 90s, accomplished the real embodiment of chips in a multi-layer package.2 Since the inception of GE’s chip-first process, several approaches have developed for embedding chips into polymer and other thin core matrices, especially with the invention of die thinning processes to a thickness of <100 µm. Notables among these processes are Fraunhofer IZM chip in polymer, Imbera’s chip in board, European Commission’s Hiding Die Project, Matsushita SIMPACT, and Intel’s Bumpless Build-up Layer (BBUL). Innovations leading to embedding chips can be encompassed by four major categories shown in Figure 1.3
Figure 1: Assumable active embedded technology.
Besides miniaturization in thickness, another key advantage in embedding actives is the reduced interconnect length. An analysis of parasitics in different package configuration was conducted by Daum at GE.2 Results show that high density interconnect (HDI) with embedded components and actives could lead to a significant reduction in R, L, C parasitics (Table 1).
Table 1: Calculation of parasitics in various packaging approaches.
The LCP Advantage
LCP has emerged as a novel dielectric material for RF packaging. The low-loss (tan d = 0.003) up to mm-wave frequency range, near-hermetic nature (water absorption < 0.04%) required for MEMS packaging, and lower cost (projected $7