By Ritwik Chatterjee, Ph.D., and Rao R. Tummala, Ph.D, Packaging Research Center—Georgia Institute of Technology
There is a need for miniaturization at the IC, module (or sub-system), and system levels. At the IC level, scaling continues as it has over the last four decades according to Moore’s Law. In addition, 3D chip stacking technology with through silicon vias (TSVs) has garnered a lot of attention recently due to its potential in improving the performance, form factor, cost, and reliability at the sub-system or module level. There is still much research and development required to bring this hetero-integration technology to cost-effective implementation with the required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system.
Although active and stacked ICs are a highly functional and important component of the overall system, it is only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely unmet by the current research in the areas of thru-Si vias (TSVs), 3D stacking, and wafer level packaging. This requires a multidisciplinary, collaborative, and global effort.
To develop 3D integration and system technologies beyond the present research activities, the Packaging Research Center (PRC) at Georgia Institute of Technology (Atlanta, GA) has teamed up with IZM Fraunhofer (Berlin, Germany) and the Korea Advanced Institute of Science and Technology (Deajeon, Republic or Korea) to develop technologies that address the present needs in TSV, 3D stacking, interposer technology, and system needs of miniaturization and monolithic integration of components. Although the initial research effort will focus on TSVs, 3D stacking and Si interposer with better electrical and thermal performance, greater system reliability, and reduced form factor and cost, it will go far beyond this to realize a truly seamless wafer system module (WSM). The WSM, as shown in Figure 1, will incorporate aspects of 3D stacking, as well as Si package with embedded passive components.
To achieve the system integration technologies proposed, we identified the technology needs in five basic areas:
In each of these areas, there is already ongoing activity by many researchers, but there are many issues that are unresolved.
Design and Test
There is a need for design tools, especially those that allow the simultaneous modeling of electrical and thermal effects from nanometer to millimeter scale. Signal switching noise in power delivery networks, hybrid equalization of signals, low cost parametric test methodologies, and novel design and structure of wiring and TSVs are other topics to be researched in this program.
Si Interposer Research
Si interposer research will focus on replacing the organic packaging by means of wafer level packaging (WLP) with TSV technologies with a Si core. We will use both typical semiconductor processing technologies (DRIE, CVD, PVD), as well as packaging technologies (dry film lamination, electroless plating, etc.) to achieve high-density wiring and I/O with better thermal and mechanical properties and reduced cost.
Low-cost TSV and Stack Bonding
There is currently a lot of research and development activity in the area of TSVs and stack bonding, however, issues of thermo-mechanical reliability and cost have not yet been resolved. Several fundamental projects are proposed within this program to improve the reliability and significantly reduce the cost of TSV technology. This includes the fabrication of novel TSV structures and geometries, novel process technologies that result in faster unit process steps or the elimination of process steps in the overall integration, and novel interconnection technologies that will result in increased reliability and reduced cost of stacking die.
Embedded Actives and Passives
Embedded active and passive technologies are a very important area of research in enabling system miniaturization. Research projects in embedded antennas, high-density and high-Q capacitors and inductors, embedded die-stack in Si cavities, and embedded actives in build0-up layers will be pursued.
System interconnection research will primarily focus on second level (substrate to board) interconnections. As we move to Si packaging substrates, the thermo-mechanical reliability of first level (IC to package) interconnections is less of a concern than second level interconnections. In the 3D-ASSM program, novel structures and processes are proposed to address the thermo-mechanical reliability of substrate to board interconnections.
In addition to the twenty-four fundamental research projects proposed in the five technology areas described, technology demonstrator test vehicles will also be designed and fabricated. These test vehicles are for the purpose of incorporating and demonstrating the technologies developed in the various research projects. The test vehicles will include 3D stack bonding, Si interposer/package, and WSM.
As part of developing the 3D-ASSM program, workshops have been held in Atlanta, Berlin, Tokyo, and Seoul, with strong participation of over 250 scientist, engineers, and managers from over 80 semiconductor IC, packaging, system and supply chain companies. A final meeting to finalize the 3D-ASSM program prior to launch is planned for October 28 and 29 in Atlanta. To discuss the program in greater detail, please contact contact Ritwik Chatterjee