While moving towards tomorrow’s high-performance 3D packages with through-silicon vias (TSV) has captured most of the attention in the industry, stacked packages and similar established approaches have many 3D advantages and are making substantial, if quieter, technical and market progress.
BY GEORGE A RILEY, PH.D, Contributing Editor
Through-silicon vias (TSV) have captured the 3D packaging spotlight, as evidenced by crowded conference sessions, a tsunami of technical papers, and an increasing buzz about how great it’s going to be — when they finally do it. Attracted by the growing demand for higher performance in less space, more than 50 companies are reportedly progressing towards commercializing TSV. The eventual winners must find paths that include acceptable prices, scalability, established supply chains, and commercial payoffs large enough to justify their investments.
Meanwhile, in the shadow of this Tower of Babbling, 3D components continue to be produced in high volume by other methods. The producers are making quieter but steady progress to improve and extend the capabilities of proven 3D approaches, or even to introduce new, potentially disruptive ones.
Die stacking, perhaps the simplest and most used 3D technology, piles up and connects a stack of die. Last year, Samsung demonstrated a stack of 16 wire-bonded NAND flash memory die in a single 1.4mm-thick package, using die thinned to 30μm with 20μm adhesive layers. Samsung developed new processes for the 16-die stack, including a new laser-cutting technology to dice the thin wafer, and a method to maintain uniformity of the thin adhesive layer. While Samsung projected no immediate commercial demand for 16-die stacks, they will use these developments to create thinner packaging for their current die stacks.
Edge bonding by creating vertical conductive tracks across the edges of the die stack is an alternative to traditional wire bonding. Edge bonding avoids the complexity of wire bonding and reduces the stack footprint, while eliminating wire parasitics that limit speed and performance.
Vertical Circuits, a technology development and licensing company, introduced high-speed jetting of conductive polymers to create stack edge bonding. The process first redistributes bond pads to the periphery of the die if needed. Die are then coated with a thin dielectric layer that insulates the edges and bond pads. The die are prepared for stack interconnection by removing the insulation from only the bond pads that will be interconnected using laser ablation.
An adhesive binds the die in a parallel or offset die stack. Edge interconnections are made by high-speed dispensing of silver-filled conductive polymer to form a conductive pillar from each exposed bond pad to the bottom of the stack. The conducting columns extend below the bottom die, creating a complete chip-scale packaged stack, ready for mounting on a board, substrate, or in a package.
Figure 1. Eight die offset stack with conductive polymer interconnections. Courtesy of Vertical Circuits, Inc.
Figure 1 shows an offset stack of eight die, each about 40μm thick, separated by 10μm thick die-attach film. They are connected to each other and to the substrate by the conductive polymer columns. The horizontal offset for conductive adhesive interconnections is only about 1/3 of that required for wire bonding.
For high-volume manufacturing, the stacks are mounted in a large array on the un-singulated substrate panel before connecting the stacked die to each other and to the substrate. Individual memory cards are singulated from the panel after molding or encapsulation. Eight die are stacked in an 0.8mm total height FBGA package only slightly larger than the die in X and Y dimensions.
Die preparation is at the wafer level. All handling and processing beyond wafer level uses gang or array methods to maximize throughput and minimize cost. Parallel processing, and using silver conductors instead of gold wires, results in lower pricing than for competitive wire-bonded stacks.
No unusual facilitation or assembly equipment is needed, so the capital investment is small.
Next Generation PoP
Package-on-package (PoP) interconnects stack packages rather than bare die, allowing an easy mixture of die types and technologies, such as memory with control electronics. Packaged components have several advantages over die. Packages are easier to handle, fully testable before assembly, and have established supply chains. However, present stacked packages cannot meet the next-generation requirements for high-density packaging, which are being driven by telephone handset needs such as reduced size, increased pin counts at finer pitch, wider memory bus, dual-channel architecture, and integrated decoupling capacitors.
Last year, Tessera developed a copper inter-package contact layer to reduce total stack height in PoP stacking. The contacts are tapered copper micro-pillars with a height of 25 to 175