by Debra Vogler, Senior Technical Editor, Solid State Technology
Dec. 1, 2008 – Sizing up a TSV market beyond the early adopters — e.g., image sensors, server DRAM, and communication/mobile Internet devices — Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation with a target cost <$150/wafer. Only two collaboration partners, Semitool and IMEC, have been made public, though other Applied partners span each segment of the TSV cost "pie" and end users' requirements (e.g., EDA tools, reliability, and design).
The company believes end-user adoption of TSV technology will be accelerated if it acts as the “glue” — working with the relevant players instead of waiting an indeterminate amount of time for the gaps in TSV technology to be filled. Statements made by Hans Stork, group VP and CTO of Applied’s silicon systems group, underscore the importance of this approach. “TSV technology will revolutionize chip designs and has great potential to expand into more sophisticated integrated memory/logic applications,” he says in a related news release. “By providing the technology and key supplier relationships, we can help accelerate the adoption of TSVs for mainstream manufacturing.”
Work with Semitool has resulted in an integrated TSV process sequence comprising TSV etch, PECVD oxide and PVD barrier/seed, and ECD copper steps, according to Sesh Ramaswami, senior director of SSG strategy in Applied Materials’ silicon systems group, in an interview with SST.
Figure 1. Applied-Semitool TSV integrated process sequence. (Source: Applied Materials; shown with permission, wafers from ITRI/Ad-STAC)
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Doing its part to contribute to lowering the total cost of TSV implementation, Applied has launched its Silvia etch tool. Brad Eaton, global product marketing manager in Applied’s etch/cleans business unit, told SST the new tool is a kind of “Swiss Army knife,” tailored to meet a wide range of integration schemes — for example, it can work with via CD and aspect ratio ranges of 1μm-100μm, and 1:1 to >25:1, respectively. Processes supported span via first (pre-CMOS silicon and post-CMOS, pre-BEOL oxide and silicon) and via last (pre-bonding metal, oxide and silicon, and post-bonding oxide and silicon). The tool is able to etch silicon and oxide in the same chamber.
Eaton said that Applied’s proprietary version of the time-multiplexed gas modulation process (TMGM, also known as the “Bosch” process) overcomes the poisoning of the etch reaction that accompanies the standard approach. In the standard Bosch process, the etch rate degrades as the etching goes deeper, resulting in a scalloped sidewall. To compensate for the scalloping, the etch rate is slowed down (or poisoned) in traditional TMGM — but cost-of-ownership is thereby degraded. Conversely, he noted, Applied’s proprietary RF and gas modulation technology has a minimal trade-off in etch rate vs. the amount of “scalloping” that occurs.
Figure 2. Minimal tradeoff in etch rate vs. scallop with Applied’s proprietary TMGM process. (Source: Applied Materials)
Besides the technical performance — a silicon etch rate that supports profile control — the new etch tool requires no consumable process kit. Two systems are at customer sites (DRAM manufacturers) in pilot production. — D.V.