IBM’s Farrell: Computational litho, scaling to 16nm

Tim Farrell, distinguished engineer at the semiconductor R&D center at IBM, discusses joint work with Mentor Graphics to implement comprehensive computational scaling. The two companies have been working together since the 130nm node; last September (9/17/08), they announced a development program for computational lithography at the 22nm node.

It is IBM’s intent to look to computation scaling to take the industry to the next couple of process nodes. One of several challenges at 16nm, noted Farrell, is that electromagnetic field effects will be unavoidable; advances in the mask fabrication process will be required to address them.



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