Thermal Test Chip

By Bernie Siegal, Thermal Engineering Associates, Inc.
A thermal test chip is usually designed to help thermal engineers answer critical thermal packaging or material questions. These chips can be divided into to basic groups &#151 one for general purpose applications and the other for thermal simulation of a very specific application chip. The former group is used for package characterization in standard or application-specific thermal environments, heat sources in multi-chip packages (MCMs), and system-level thermal studies. The latter group targets specific chip designs that have complex heat generation topologies &#151 such as multi-core processors or system-on-a-chip designs &#151 and are designed on a one-for-one basis. Thermal test chips for the latter group are usually designed by the manufacturer of the corresponding application chip as a tool to help their customers get started on the thermal design efforts well before the application chip design and fabrication is done.

The general-purpose thermal test chip must meet the following key requirements:

  • Maximum possible heating area relative to chip size.
  • Uniform temperature profile across heating area.
  • Low temperature coefficient for heating source.
  • Temperature sensor in center of chip.
  • Simple-to-use temperature sensor(s).
  • Multiple temperature sensors for a temperature profile across chip surface.
  • Kelvin Connections (i.e., 4-wire connections) for improved measurement accuracy.
  • Chip size that closely approximates the chip being simulated.

    This paper describes a thermal test chip that meets these requirements in the simplest manner possible. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements.

    The thermal test chip described herein is based on a unit cell that has two resistors and four diode temperature sensors in each cell (Figure 1). The resistors are deposited metal film resistors that have resistance values suitable for laboratory measurements. Each resistor is 7.6O nominal, a value chosen to better realize a wide power dissipation range using normally available laboratory power supplies. The two resistors are laid out to occupy 86% of the available area within the electrical contact pads, thus conforming to the JESD51-41 85% coverage requirement; the resistor layout is shown in Figure 2. Note that each resistor has two contacts at each end. One contact at each end is used for the power connection while the other is used for measurement; this 4-wire Kelvin Connection eliminates contact resistance problems during voltage measurements across the resistor. The metal film resistors offer better resistance uniformity a (typically =±5%) cross the wafer and =±2% across a 4


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