April 27, 2009 – Novellus has been sending out quite a bit of PR lately describing its technologies and processes targeting 32nm semiconductor manufacturing: dielectric diffusion barriers, process defect detection for Cu interconnects, and most recently a tungsten plug fill CVD process.
The latter, a reduced-temperature (<395°C) CVD process, directly addresses challenges in achieving void-free fill that meets the International Technology Roadmap for Semiconductors‘ (ITRS) requirements for 32nm devices — specifically, aspect ratios >20:1 for stacked capacitor DRAM contacts, and >10:1 AR for logic devices. Achieving void-free fill that meets required low electrical properties in such aggressive features will be hard to do using conventional CVD tungsten deposition techniques, the company says.
Cross-sectional TEM images comparing 32nm 18:1 aspect ratio contacts processed using standard and Novellus; CoolFill CVD. (Source: Novellus)
Its answer: the CoolFill process, which minimizes mass transport effects responsible for void formation. Used in concert, a “pulsed nucleation layer” (PNLxT) technology and “multistation sequential deposition” (MSSD) architecture on the company’s Altus CVD system, simultaneously deposit nucleation and fill layers at different temperatures. Combining lower-temperature feature fill with higher-temperature bulk fill mitigates the deposition rate and throughput reductions seen in conventional CVD systems. (The video animation below shows how the process works.)
The CoolFill “provides a larger process window to achieve void-free tungsten fill, thereby simplifying our customers’ integration challenges as they scale their devices to the next generation technology node,” said Michal Danek, senior director of technology for Novellus; direct metals business unit, in a statement. The combination of CoolFill technology with PNLxT and multistation platform architecture “will extend tungsten to the 32nm technology node and beyond.”
Animation showing how Novellus’ CoolFill CVD tungsten plug fill process is made possible through a multi-station sequential processing architecture. (Source: Novellus)