Toppan’s Kalk: 28nm tapeouts proceeding according to plan

by Debra Vogler, senior technical editor, Solid State Technology

Toppan Printing Co. Ltd. has established a new photomask manufacturing process at its photomask facility in Asaka, Japan, to support 32nm and 28nm semiconductor device production, through an ongoing joint development project with IBM. Photomasks produced at this site are compatible with those produced at IBM’s photomask facility in Essex Junction, VT, and have been qualified by IBM.

“We now have the final toolkit and have done the fine tuning of the process in Burlington,” Franklin Kalk, CTO at Toppan Photomasks, told SST. 32nm test chips are already being taped out, and by 2H09 and into 1H10, “numerous customers will be ready for production tapeout for 32nm bulk CMOS,” he said. Bulk CMOS 28nm test chips for logic are anticipated to proceed in 1H10 with bulk production taking place in 2H10. “There is strong pull for this technology,” which Kalk finds encouraging.

The fundamental difference between photomask processes at 45nm-40nm and at 32nm is the mask material, Kalk explained. “Instead of using molysilicide, we’re using an opaque molysilicide over glass [OMOG] at 32nm,” a material developed jointly by ShinEtsu and Toppan and manufactured by ShinEtsu, and now also being used for Toppan/IBM’s 28nm process. “The material is easier to process than chrome because moly is easier to etch,” he said (see Figure) — chrome requires a chemical etch, with all the attendant issues that go with it. Additionally, making molysilicide opaque instead of partially transmitting is a simple adjustment to the oxidation state of the material, “a simple chemistry change in the deposition of the film,” he explained. OMOG also has extremely good resolution linearity properties, Kalk added.


Advantages to an “OMOG” binary mask replacing MoSi halftone at 32/28nm: Easier to etch, lower defect density, and shorter manufacturing cycle time. (Source: Toppan Photomasks)

Toppan’s collaboration with IBM began in 2005 at the 45nm node, and has progressed to the highly specialized masks required to support source mask optimization (SMO) at the 22nm node. SMO, the co-optimization of the illumination source and mask pattern, results in a lithographic solution for building more advanced semiconductor devices than would be possible with conventional lithographic techniques, and is expected to extend immersion lithography through and beyond the 22nm node. Toppan Printing plans to launch volume production of SMO-applied photomasks in 2011, leveraging technical assets accumulated by the collaboration with IBM.

Asked about the eventual readiness of EUV lithography, Kalk’s personal belief is that EUV lithography more than likely will not be ready for production until the 16nm logic node, and very few companies will be able to afford it — so double-patterning will be used for the next several years. “That’s a choice a lot of companies will make,” he told SST. “EUV might get injected early on for one layer on one part, but if I had to bet, it would be run in parallel with an existing process that is already known to work — allowing EUV to mature with less risk.” — D.V.

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