by Debra Vogler, senior technical editor, Solid State Technology
May 12, 2009 – SEMATECH recently announced a collaboration agreement with photoresist manufacturer Tokyo Ohka Kogyo Co. Ltd. (TOK), in which TOK joined SEMATECH’s Resist Materials and Development Center (RMDC) at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The RMDC’s mission is to develop resist and materials for 22nm patterning technologies and beyond, consisting of both extreme ultraviolet (EUV) exposure capability and a portfolio of sponsored university research programs. TOK will team with researchers at SEMATECH to develop and demonstrate EUV materials and resists for use at the 22nm node and beyond.
The top three challenges for EUV resists are resolution, sensitivity, and linewidth roughness (LWR) — in particular, simultaneously meeting the resolution (22nm), and sensitivity targets (10mJ/cm2 or less) along with obtaining an LWR on the order of <2nm, 3σ, according to Bryan Rice, director of lithography at SEMATECH. "We've been able to achieve the sensitivity and resolution targets separately, but we haven't been able to achieve the LWR target," he told SST. “No single material, even without restriction on resolution and sensitivity, has been able to achieve LWR — that’s the main challenge for EUV resists,” and then meeting all three simultaneously, he explained.
At the RMDC, resist and materials suppliers have access to SEMATECH’s two micro-exposure tools (METs) located at the University at Albany’s College of Nanoscale Science and Engineering and University of California at Berkeley, and can participate in focused, cooperative R&D with SEMATECH member companies. Companies also have access to the several metrology tools located in SEMATECH’s RMDC. “The RMDC brings together the critical capabilities needed to enable manufacturable EUV,” said Rice. “Partnering with resist suppliers such as TOK will accelerate EUV resist development and, in turn, will support timely EUVL introduction.”
Assessment of EUV resist readiness for 32nm hp
SEMATECH’s RMDC made a quiet splash at this year’s SPIE Advanced Lithography Conference, presenting a paper (“Assessment of EUV resist readiness for 32nm hp manufacturing, and extendibility study of EUV ADT using state-of-the-art resist;” Proc. SPIE, Vol. 7271 727124-1) with resist readiness/process feasibility data for 32nm half-pitch using EUV’s alpha demo tool (ADT) used by the RMDC.
Figure 1: Imaging results of a 60nm thick SMT03 on the ADT top without and bottom with an underlayer demonstrate an improved process window using a spin-on underlayer. (Source: SEMATECH)
The researchers were able to show that the resolution limit improved for a given resist platform from 28nm hp to 26nm by using a spin-on underlayer (Figure 1). LER and LWR were 3.2nm and 4.8nm, respectively, when using a 60nm thick resist film on a hardmask wafer without using an underlayer, but the values improved to 2.9nm and 4.3nm, respectively, when using the SMTUL1 underlayer (Figure 2). — D.V.
Figure 2: Process window for a 30nm hp pattern with a 60nm thick resist on an underlayer on a hardmask wafer. (Source: SEMATECH)