Yale, SRC push ferroelectric DRAM

August 24, 2009Researchers from Yale and the Semiconductor Research Corp. (SRC) say they have found a way to apply ferroelectric gate material to a DRAM cell (i.e., a FeDRAM) to create a more simply structured, highly scalable, longer-lasting and lower-power-consuming device with multibit storage capabilities comparable to flash memory.

Work to develop FeDRAM devices that eliminate the need for a memory cell capacitor isn’t new, but Yale researchers note they’ve got data showing properties that could “produce meaningful cost and performance benefits to global DRAM makers and their customers,” according to Yale prof. T.P. Ma, in a statement. With FeDRAM a device can be programmed and erased by a gate voltage pulse; charge retention is >1× longer than conventional DRAM requiring much less refreshing. Cell structure is similar to a CMOS transistor with a circuit architecture similar to flash memory, so it’s manufacturable with existing fabrication techniques and toolsets. And it seems to be very scalable, something existing DRAM technology is not due to storage capacitance in a given area, added Kwok Ng, director of device sciences at SRC. “We see the potential for greater scalability with FeDRAM, extending the benefits well into the future,” he noted.

The Yale/SRC work will continue toward demonstrating FeDRAM cells, simple building block circuits, and pathways for scaling, with optimism for production readiness but in an unclarified “foreseeable future.”


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