Silicon nanowires become industry-compatible

by Vincent T. Renard and Vincent Jousseaume, CEA-Leti

Executive overview
There is every reason to be optimistic about the future of information processing because solutions are emerging to add new functionalities, such as sensors, peripheral to the computing core of microprocessors. These new functionalities implemented above ICs in the interconnection levels, or even in the packaging, could allow information-processing systems to interact directly with the environment in absence of direct user input. Interestingly, the ability to vary silicon’s resistance by a large degree, combined with small device dimensions, may again be a key to this qualitative, rather than quantitative revolution.

February 17, 2010 – As a semiconducting material, silicon’s resistance can be varied significantly by increasing current-carrier density either permanently by doping, or temporarily by applying an electrostatic potential. Using this property and CMOS technology, the microelectronic industry has been able to produce binary information-processing integrated circuits. Miniaturization, which has driven the increase in performance of such ICs, may soon reach a limit as the size of constituting devices evolves toward atomic scale. In this context, rod-shaped silicon nanocrystals (silicon nanowires) have shown the potential needed to realize these new functionalities. A well-known example is the silicon nanowire-based pH sensor developed at Harvard [1]. The nanowire was chemically functionalized to provide a surface that can undergo protonation and deprotonation, inducing changes in surface charges depending on the pH of the surrounding solution. This functionalization modifies the nanowire resistance by changing the electrostatic potential. Because of the high surface-to-volume ratio of the nanowire, the conductance of the device is very sensitive to subtle change in surface charges, and therefore to the pH.

The ability to dope silicon could also be used in nanowire-based devices using nanoscale pn junctions, such as with solar cells [2]. Here again, the high surface-to-volume ratio is crucial because solar cells need large surfaces to collect light efficiently and small volume to avoid carrier recombination. Many other potential applications have already been identified; it is therefore surprising that they haven’t yet been developed as commercial products. As usual, the use of new material in devices involves trade-offs. In the "plus" column are the potential for low cost, ease of fabrication, and an incredible variety of potential applications of silicon nanowires from electronics to optics, chemistry, and NEMS. In the "minus" column is that the production of silicon nanowires has remained incompatible with CMOS technology and therefore, nanowires are impossible to integrate above ICs.

Silicon nanowire fabrication: bottleneck to industrial use

The synthesis of silicon nanowires is a 40-year-old subject. Despite the tremendous amount of work dedicated to this challenge, fabrication surprisingly still relies on the same original recipe. This recipe uses a liquid gold nano-droplet to catalyze the growth from a gaseous precursor of silicon (typically SiH4). However, gold is prohibited in CMOS microelectronic factories because it degrades electrical properties of silicon. This is why manufacturers have been reluctant to use nanowire-based technology.

There have been recent attempts to use other CMOS-compatible metal catalysts (for example, copper), but this metal forms a liquid alloy with silicon only above 800°C — too high to be compatible with CMOS processing (TCMOS <450°C). It was recently discovered that the copper-based catalyst may remain in the solid state during growth, generating hope for a low-temperature synthesis. Unfortunately, soon after this discovery, diffusion during incubation (catalyst preparation) was identified as setting a fundamentally lower limit on the growth temperature using copper (T>500°C) [3]. Among the community of researchers, the pessimists thought that silicon nanowires would never be transferable to industry due to the fabrication problem, and the rare optimists thought that a change in paradigm was necessary to achieve that goal. The industrial use of silicon nanowires seemed to be stuck in a dead-end until the concept of "chemically activated incubation" [4] was discovered at CEA-Leti.

Chemically activated incubation

It is well documented that the presence of oxygen is detrimental to silicon nanowire growth when gold is used as a catalyst. In recent decades scientists have therefore been trying to eliminate oxygen from their growth chamber because the vast majority of experiments were performed using gold. Naively, researchers conducting the first experiments using non-gold catalysts at CMOS-compatible temperatures repeated this oxygen hunt applying the old empirical knowledge. Using the traditional method, the silicon precursor SiH4 was then decomposed on the metal particle and silicon incorporated into the particle. Here, everything was controlled by diffusion of silicon in a metal-rich particle, which can be quite slow at low temperature.

Click to Enlarge
Schematics and yield of the a) diffusion-based incubation vs. b) chemically-activated incubation methods at 400°C.

In the case of copper, the actual catalyst is a copper-silicide (Cu3Si) and even the formation of this catalyst (incubation) takes an extremely long time at CMOS-compatible temperatures and prevents nanowire growth (see figure). We found that oxidizing copper before growth is extremely positive for nanowire synthesis at temperatures as low as 400°C, which is exactly opposite the result obtained with gold. This is due to the very high reactivity of cuprous oxide, which chemically activates the formation of Cu3Si. This observation, therefore, demonstrates that the synthesis temperature of silicon nanowires is limited by catalyst preparation, rather than by the growth itself.


Chemically activated incubation solves the first prerequisite for industrial transfer of silicon nanowires. Notably, our research was performed in the CEA-Leti clean room with an industrial tool on 200mm wafers so that our processes can be transferred to industry. Nevertheless, achieving CMOS compatibility is not the single issue to be resolved for a complete industrial transfer. For example, some applications (e.g., vertical transistors in interconnection) need control of the growth direction. Until now, the only available solution to this problem has been transferring the crystalline information from the substrate to the nanowires using epitaxy. However, achieving growth perpendicular to the substrates using this method requires substrates oriented in a particular crystallographic direction, which can be particularly expensive (i.e., industry-incompatible). Here again, being able to grow nanowires in any direction and on any substrate will probably necessitate a conceptual leap to exit the apparent dead-end. Other, simpler applications such as solar cells don’t need precise control of the growth direction. Determining whether integration of those can be achieved clearly is the most promising next step.


Vincent T. Renard received his PhD in nanosciences from Institut National des Sciences Appliquées in Toulouse (2005) and is a research associate at CEA-Leti, MINATEC, Grenoble, France.

Vincent Jousseaume received his PhD in materials science from the U. of Nantes, France (1998) on conducting polymers and a HDR (Habilitation à diriger des recherches) on thin films in microelectronic from the Polytechnics Institute of Grenoble, France (2006). He is a senior scientist at CEA-Leti, MINATEC, 17 rue des Martyrs, 38054 Grenoble, cedex 9 France; e-mail;


[1]. Y. Cui, Q. Wei, H. Park C.M. Lieber, "Nanowire Nanosensors for Highly Sensitive and Selective Detection of Biological and Chemical Species," Science, 293,1289 (2001)
[2]. B. Tian, "Coaxial Silicon Nanowires as Solar Cells and Nanoelectronic Power Sources," et al., Nature, 449, 885 (2007).
[3]. B. Kalache et al., "Observation of Incubation Times in the Nucleation of Silicon Nanowires Obtained by the Vapor–Liquid–Solid Method," Jpn. J. Appl. Phys., Part 2 45, L190 (2006).
[4]. V.T. Renard, et al., "Catalyst Preparation for CMOS-compatible Silicon Nanowire Synthesis," Nature Nanotechnology, 4, 654 (2009).


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