by Stefan Wurm, associate director of lithography, SEMATECH
This article is a companion piece to the author’s discussion about the choices to be made among lithography options for the 22nm half-pitch node, in the February issue of Solid-State Technology.)
February 5, 2010 – In 2009, the International EUVL Symposium Steering Committee  ranked the top three critical issues/focus areas for extreme ultraviolet lithography (EUVL) as:
- Mask yield and defect inspection/review infrastructure
- Long-term reliable source operation with 200W at the intermediate focus (IF)
- Resist resolution, sensitivity, and line edge roughness (LER) met simultaneously
EUV mask yield and its defect inspection/review infrastructure were perceived as the most critical issue for EUVL to be introduced into high-volume manufacturing (HVM). Reliable high-power EUV sources continue to be a concern, but recent progress has raised confidence that EUV sources for pilot line production, with ~100W at the IF, will be available with the first exposure tools in the second half of 2010. However, reliable high power sources that can support HVM requirements remain a significant risk. Progress in resist materials continues; resolution and sensitivity targets for 22nm hp HVM have almost been met while post-exposure line width roughness (LWR) reduction techniques demonstrate that a 2-3nm LWR at the required resolution and sensitivity is attainable.
Optical insurance policies
Immersion lithography is supporting current manufacturing, and lithography engineers continue to explore the potential for extending it through various double patterning/pitch division techniques to sub-32nm hp nodes . The main challenges in extending 193nm immersion lithography using 1.35 NA tools for double patterning are simply: (1) achieving the required feature resolution (target CD); (2) achieving this over the full wafer (CD uniformity control); and (3) placing patterns with very high precision on top of each other (overlay control). If those three challenges can be met with a process window that is large and stable enough to support manufacturing requirements, then immersion double patterning can be a viable insurance policy that could allow chip manufacturers to stay on their roadmap even if EUVL is delayed.
Cost-of-ownership remains a major concern for using double patterning techniques; it will be even more so as feature sizes shrink and design challenges and the number of masks per layer dramatically increases. Therefore, double patterning techniques, of which there are many more now than a few years ago, will likely be used in a very opportunistic way by making use of all forms of pitch division on a layer-by-layer basis . For example, overlay critical layers will likely be defined using self-aligned double patterning (SADP) methods, whereas a negative tone pitch division process might be used to define trenches with a better process window.
Meeting these challenges will be possible only with a more extensive use of computational lithography tools as design rules become more complicated. Every available knob will have to be used to maintain a manufacturable process window. Source mask optimization (SMO)  will also play a critical role with both of its key components: computational lithography and design optimization (the software) and pixilated diffractive optical elements and masks (the hardware). While inverse lithography methods may help solve a lithography challenge by enabling process windows for low k1 lithography, they will also create a new inspection challenge: effective and cost-efficient mask inspection for inverse lithography will be a key issue if inverse lithography is to be widely used by chip manufacturers.
The three basic double patterning/pitch division approaches — litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and sidewall spacer — have now mushroomed into a plethora of different methods that use, for example, different freeze methods (chemical and thermal), darkfield and brightfield imaging using positive and negative tone development, and dual-tone double patterning. Methods differ in how trenches and vias are defined by combining various dual line and cross line patterning processes. As future innovations in imaging and optical materials, process controls, and computational models increase the menu selection for double patterning, customized use of double patterning may be possible at 22nm hp and below.
The author would like to acknowledge his colleagues in SEMATECH’s lithography division and at GlobalFoundries, Intel, and Samsung for valuable discussions.
Stefan Wurm received his doctorate in physics from the Technische Universität München, Germany and is the associate director of lithography (on assignment from Globalfoundries) at SEMATECH, 257 Fuller Road, Albany, NY 12203, USA; ph.: 518-649-1000; e-mail: firstname.lastname@example.org.
 2009 International Symposium on Extreme Ultraviolet Lithography, October 18-21, 2009, Prague, Czech Republic.
 6th International Symposium on Immersion Lithography Extensions, October 22-23, 2009, Prague, Czech Republic.
 S. Sivakumar in ref. 2.
 D. Medeiros in ref. 2.