At the Electronic Components & Technology Conference (ECTC) this month in Las Vegas the CPMT (Components, Packaging and Manufacturing Technology) Society of IEEE bought out their long time partners ECA (formerly EIA) and now have sole financial sponsorship of this highly regarded global conference.
ECA’s Bob Willis turns over the ECTC Conference
to outgoing IEEE CPMT President Bill Chen
STATSChipPAC expanding presence in eWLB
STATSChipPac, a member of the consortium which includes Infineon (the inventor of the technology), ST Micro and ASE, has been working diligently for the last few years to make the technology now generically known as eWLB [embedded wafer level BGA] the eventual successor to the BGA package.
|Cross section of the eWLB|
Raj Pendse,VP Flip Chip product line, indicates that STATS did 30K eWLB wafers in Q1 of 2010. Since all the necessary 300 mm equipment is not yet in place 300 mm wafers are currently being cored to 200 mm in order to run them through the current production line. STATSChipPAC plans on having full 300 mm capacity in place by 4Q 2010. According to Deputy Director of the Technology Division Seung Wook Yoon, yields are already “….approaching the high 90’s “
|Raj Pendse (left ) and Seung Wook Yoon|
Pendse commented that STATS has qualified a multidie (SiP) eWLB process and stacked ( 2 sided ) eWLB processes are being developed. Pendse sees eWLB as“…a bridge between current packaging solutions and full 3D stacked TSV solutions which are still a few years off”
Yoon indicates that eWLB packages are being used for baseband parts now and will be commercialized in Rf transceivers next. Pendsej sees the first multi die products being transceiver + connectivity chips and Rf devices.
ASE is the main second source for eWLB. Infineon has also licensed Portugal startup, Nanium (ex Quimonda / Infineon / Siemens)and others.
While there were more than 25 presentations and three short courses dealing with aspects of 3D IC integration (i.e. 3D with TSV) there were no commercial announcements of any significance this year. While Cu/Sn eutectic still appears to be the bonding technology of choice for OSATS like Amkor, STATSChipPAC and ASE, institutes continue to unravel the details of copper – copper bonding. It now appears clear from the work at Institutes such as CEA Leti and RTI (Research Triangle Institute) that thermocompression (TC) bonding and direct copper bonding lie on a continuum where direct bonding has the lowest temperature requirements and the highest roughness requirements (0.5 nm RMS) while TC bonding appears at the other end of the spectrum. The Leti group also extended direct bonding technology to tungsten which is used in several processes as the conductive TSV fill material.
Doublecheck thin wafer handling solution
Doublecheck Semiconductors, working with Disco and the Fraunhoffer IZM claims to have developed technology that enables standard silicon wafers to be thinned down to less than 100µm without the use of temporary adhesives, carrier wafers or other supports. CTO Florian Bieck indicates that “..this allows for backside-processing of TSV-Wafers utilizing standard processes and equipment without any temperature limit to PECVD, plasma etch or solder-reflow by the handling solution”. Managing Director Sven Spiller adds that their solution “…enables TSV wafers to be tested at wafer-level from both sides at the same time”
Doublecheck’s wafer design and process is based on existing equipment and processing from DISCO’s "TAIKO Series” . Doublecheck applies a patented slit design to the "TAIKO" wafer at the outer rim. This enables handling and processing thin wafers down to 50µm and less with standard machines in existing manufacturing lines. In a joint development program the three partners produced samples of 60µm thick wafers which show a complete RDL (redistribution layer) and bumping on the wafer backside.
Sven adds that “…together with Fraunhofer and DISCO we started 300mm development and we will offer our customers sampling and engineering services for TSV wherever needed."
|Doublecheck Thinned wafer|
TOK’s Zero Newton thin wafer handling solution
TOK’s Chris Rosenthal indicates that they have enhanced the thermal performance of the temporary adhesives used in their Zero Newton thin wafer handling systems. They claim to be comfortable with backside processing temperatures as high as 280 °C. They worked on a joint development program with the IBM 3D technology group in Yorktown Heights (Andry, Knickerbocker et. al.) who co-authored their presentation at ECTC.