IITC Day 0: Short course reflects interconnects’ maturity

by Michael A. Fury, Techcet Group

June 7, 2010 – The 2010 International Interconnect Technology Conference (IITC) is back at the Hyatt Regency in Burlingame, CA after its first overseas venue in 2009 in Japan. This 13th IITC conference kicked off today with 65 attendees in an all-day "short course" featuring six speakers covering a variety of interconnect-related topics.

In the early days of IITC, the short course typically comprised a series of talks on individual process steps, serving as a tutorial for new semiconductor process engineers and a review for experienced engineers or those taking on new assignments. I found it striking today that the agenda had only two talks that might be considered unit process-focused (lithography and plasma etch). These talks, like the other four, took a high level holistic view of interconnect process, materials, systems design, and future needs. I believe this is a reflection of the greater level of maturity that interconnects have achieved over the past decade.Click to Enlarge

Krishna Saraswat of Stanford University spoke on the options, challenges, and advances toward future interconnects. The discussion included carbon nanotubes (CNT) and graphene, optical interconnects, and 3D integration. Optical wires offer the greatest leverage for longer global interconnects requiring higher bandwidth, while CNT makes better sense for local interconnects. Variations on 3D integration will be the enablers for maintaining and even exceeding Moore’s Law through multi-core system design rather than device shrinks and faster clock speeds.

Steven Demuynck of IMEC talked about advanced patterning techniques for interconnect scaling, specifically 193nm double patterning and 13.6nm EUV. Double patterning is required for 32nm half pitch, with litho-etch-litho-etch (LELE) being the most straightforward. EUV will allow a return to single-patterning mode at 22nm half pitch.

Nicolas Possémé of CEA-LETI reviewed the challenges of plasma processing for porous SiOCH patterning in advanced interconnects. After reviewing the variations under development, he concluded that metal hard mask integration offers the best option beyond 45nm for compatibility with porous SiOCH materials.

Ron Ho of Oracle’s Sun Labs talked quite enthusiastically about interconnect design considerations for multi-core processors. The underlying goal is to make off-chip I/O as inexpensive and effective as on-chip I/O, thus producing the "moral equivalent" of a really big chip. Upon concluding his talk, he dashed off to his daughter’s violin recital; we assume she was exceptional.

Bari Biswas of Synopsys spoke on modeling of interconnect process variation, and concluded that 3D integration is attractive for maintaining effective device density. The introduction of new device structures will bring with it the challenge to generate new modeling extractions for process variability specific to their process flow and material sets while maintaining the accuracy that has been developed for modeling of current structures.

Geoffrey Burr of IBM Almaden Research went over the technology gap for storage-class memory. The explosive growth of data farms and the amount of online data that they keep available is not sustainable using hard disk technology. Burr reviewed all of the major alternatives to current DRAM, SRAM, and flash memory that is currently in development, with an eye toward meeting the challenge of storing vast amounts of data online significantly lower power consumption than current data farms. It’s still to early to pick the winner(s) in this race, but phase-change memory is his personal favorite.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail mfury@techcet.com.

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