by Larry Smith, 3D integration, reliability & product interlock, SEMATECH
July 13, 2010 – Management of mechanical stresses is one of the key enablers for the successful implementation of 3D integrated circuits using through-silicon vias (TSVs). Copper-filled TSVs and wafers thinned to a few tens of microns modify the stress profiles in the silicon, and may exacerbate the stresses introduced by tier-to-tier bonding and chip-package interactions. These stresses have the potential to modify device characteristics, affecting functional and parametric yield and reliability. The stress-related impact of the processing done at the various companies in the manufacturing supply chain needs to be characterized and shared, and designers need a DFM-like solution for managing stress.
To address the need to simulate and measure the stresses being created by 3D IC fabrication processes, SEMATECH and Fraunhofer IZFP hosted a follow-up meeting, “Second workshop on stress management for 3D ICs using through silicon vias" in conjunction with SEMICON West on Tuesday, July 13. More than 40 technology managers from 27 companies and institutions in the US, Asia and Europe gathered to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.
Keynote speaker Riko Radojcic from Qualcomm presented a stress management for 3D TSV stacking technologies intended to support a DFM-like solution that would take stress modeling out of a T-CAD realm, and enable design entities to quantitatively model stress implications on their designs. The proposed flow is a blend of traditional FEA based tools used at package level, specialized FEA tools used to model the effects of mechanical stress on device performance, and a compact model based “stress hot spot" checker.
In a series of invited talks, other speakers discussed the following:
- A perspective on multi-simulation flow for stress assessment and a potential approach for addressing the various relevant interactions was shared by Mentor Graphics’ Valeriy Sukharev (“3D TSV Technology: Stress assessment for chip performance")
- Ehrenfried Zschech from Fraunhofer IZFP presented on the need for multi-scale materials characterization and techniques for nanometer-scale materials characterization (“Multi-scale simulation flow and multi-scale materials characterization for stress management")
- Strategies to mitigate TSV induced stresses and simulating the effect of mechanical stresses on Si devices and structures was shared by IMEC’s Pol Marchal (“TSV-induced stress modeling")
- Synopsys’ Xiaopeng Xu presented on 3D TCAD modeling for stress management (“Modeling TSV stress impact on performance and reliability")
- Robert Geer from the College of Nanoscale Science and Engineering at the U. of Albany showed comparison of micro-Raman measurements and stress modeling of copper TSVs (“Profiling of process-induced stress in Cu TSVs for 3D integration")
- A summary of the Japanese ASET program research on stress from wafer thinning, microbumps, and TSVs was presented by Mitsu Koyanagi from Tohoku University.
In the afternoon, a working session focused on reviewing the required material properties, measurement techniques, and corresponding simulation use modes to support the proposed DFM flow.
A third workshop will be held at SEMICON Europe in the fall (Oct. 20), hosted by Fraunhofer IZFP in collaboration with SEMATECH, to focus on multi-scale characterization and multi-scale materials and parameters. The workshop will feature invited talks reviewing the methodology and conclusions from the previous workshop — including tables of required material properties, measurement techniques, and corresponding simulation use modes — and assess the industry’s current approaches to this problem. There will also be a working session to establish a proposal for a complete calibration flow for intra-channel stress components of the test chip devices, based on a direct comparison between simulation and experiment.
SEMATECH and Fraunhofer IZFP have launched a wiki site to provide a forum to the community to discuss the issues raised in these workshops.
Larry Smith is a member of the technical staff at SEMATECH, responsible for 3D cost and yield modeling and reliability. He previously worked on copper low-k reliability and process integration. Prior to joining SEMATECH, he worked on high density interconnect for packaging applications, managing the design group for thin-film-on-laminate BGA substrates at Kulicke & Soffa, and managing programs on multi-chip packaging at MicroModule Systems, Dell Computer, and MCC. He received his Ph.D from the University of Illinois-Urbana. E-mail: email@example.com.