Simple wet cleaning improvements can meet new silicon surface preparation criteria

(September 28, 2010) — Robert Pagliaro, RP Innovative Engineering Solutions, demonstrates that simple but effective enhancements to wet clean steps can help achieve more stringent surface preparation and reduce complexity, cost of ownership (COO), and environmental concerns associated with existing methods. Contamination left or caused by cleaning and drying steps can adversely affect wafer yields.

Continuous improvement methodology; new materials; and innovations in device, process, and equipment designs have stretched the limits of silicon-based devices into the 2010s. New device technologies springing from these breakthroughs bring along more stringent requirements for contamination levels and thermal budgets. The new surface preparation criteria challenge state-of-the-art wet cleaning technologies developed at world-renowned institutions like IMEC and Tohoku University (Dr Ohmi’s facility). Similar to the era when their ingenious cleans replaced the long-running RCA cleans in the 1990s, significant changes may be required again to meet these tougher specifications in the silicon wafer and device manufacturing arena.

New challenges for silicon device wafer wet cleaning

For over 20 years, the leading-edge wet cleaning experts at the Ohmi and IMEC technology centers have continued to pave the way for achieving the surface preparation specifications required to keep pace with advancing silicon-based device technologies. Current device technologies demand surface contamination tolerances in the parts per trillion (ppt) regime, lower thermal budgets for processes like silicon epitaxy require bake temperatures to be < 800°C, and for silicon consumption per clean to be <0.1nm.

The best manufacturing cleaning sequences may fail under these heightened constraints. The cleaning efficiency of their dilute chemistries, even combined with the use of tera-bit chemicals, may not be able to meet the ppt contamination requirements. A pristine and stable H-terminated silicon surface termination is required to enable the low thermal budget requirements for many thermal processes. Peroxide and ozone-based chemistries inherently consume more than the 0.1nm of silicon per clean as defined in the ITRS roadmap.

Cleaning efficiency

Most of the current wet cleaning processes used in manufacturing environments still terminate the silicon with a native/chemical oxide layer. This native or chemical oxide harbors a dominant portion of post-clean contamination. Efforts have been mad to purify traditional wet cleaning chemicals such as ammonium hydroxide, hydrochloric acid, sulfuric acid, hydrofluoric acid and hydrogen peroxide. Tera-bit grade chemicals are now readily available. Chelating agents and additives, like EDTA and TMAH, as well as surfactants, are commonly used to reduce contamination in wet cleaning chemistries. H2O2, HCl, and alcohols are also commonly added in dHF mixtures to suppress contamination. While these can be somewhat effective, the main ingredient in these mixtures, ultra-pure water (UPW), still contains dissolved impurities that impregnate the chemical oxides or terminate on the silicon surfaces following cleaning sequences. These contaminants negatively affect oxide (ozone or peroxide-based mixtures) and non-oxide (dilute HF) terminating wet cleaning sequences.

Oxide and hydride silicon surface termination

Oxide-terminating cleans suffice for processes that don’t restrict a subsequent high-temperature process and are tolerant to silicon loss, but this tolerance is becoming very limited. Even in processes where it is still acceptable, dissolved impurities like oxygen (DO), carbon dioxide, total organic carbon (TOC), and silica in standard UPW can have a detrimental effect on the oxide integrity and other electrical properties. Interstitial carbon can also be diffused into the silicon when thermally processed. Dissolved organics in UPW must be dramatically reduced to improve the purity of these chemically grown oxides.

Hydrogen-terminating cleans, which are now in higher demand, are far more challenging due to the difficulty in creating a pristine and stable H-terminated silicon surface. Three primary hydride structures formed on the silicon surface (mono- , di- , tri-) all have different binding energies and are mostly controlled by the silicon’s crystalline orientation. SiHx terminations suit many processes due to their ability to be dissociated at low temperatures (500° to 550°C), accomodating thermal budgeting. A HF last process is currently the only viable method to achieving this with wet cleaning. The Ohmi and IMEC institutions each defined what they believe to be the best wet cleaning sequences [1] to achieve all of the silicon surface criteria, both of which are short sequence (2-4 steps) using ultra-dilute chemistries and terminating with a dHF-based mixture. Both of these well-developed and characterized process sequences work well in a controlled laboratory environment, but there are severe challenges when trying to implement these into a manufacturing mode. Achieving 100% SiHx terminations using a dHF wet cleaning process is virtually impossible. Minimizing the queue time between the wet clean and the subsequent process is critical due to the inherent reoxidation of the silicon surface when exposed to air. Exposure of the SiHx surface to air also permits organic contaminants to adhere.

Similar to oxide-terminating cleans; the dissolved impurities in UPW have a dramatic influence on the dHF process’ ability to provide a pristine, stable H-terminated silicon surface.

Silicon consumption

Meeting the ITRS surface preparation requirement of consuming less than 1A of silicon per clean poses the most difficult challenge for wet-clean gurus. A single monolayer of oxide growth triples this criterion. To remove metals, organics, and particles without using either H2O2 or O3 based chemistries defies the current wet cleaning protocols. Even the best IMEC and Ohmi cleans require these oxidizers. Aside from something completely new in wet cleaning chemistries, the only practical panacea seems to be to assure near 100% photoresist removal in the plasma ashing process and depend on a very pure and effective dHF mixture (with non-oxidizing additives) to remove all contaminants.

Silicon wafer drying methods: additional challenges

Along with the wet-clean and rinse challenges, there is evidence that silicon wafer drying methods that use IPA are creating unacceptable organic contamination levels. Detailed studies qualitatively and quantitatively assess this [2]. Residues following Marangoni and IPA vapor drying have shown to severely affect electrical performance for gate oxides <5nm [3]. Residues can blanket the wafer surface after H-terminated cleaning, bearing a negative impact on critical front-end processes like low-temperature Si and SiGe-based epitaxy, poly-Si stacks, and metal deposition.

With lower surface contamination tolerance, IPA-assisted drying’s benefits are outweighed by the contamination post-drying residues cause. Other non-chemical drying methods need to be enhanced or developed.

Figure 1 is from reference 4 and represents native oxide growth as a function of time in room temperature air and ultrapure water with different dissolved oxygen levels.

Achieving those demanding surface preparation goals

With the key issues with newer surface preparation criteria identified, we can discuss simple enhancements to existing leading-edge wet cleaning technologies can will overcome them. The core process engineering work and recipes that the Ohmi and IMEC camps have developed offer a great basis, but are not a complete set of instructions for use in a device manufacturing facility.

Thorough investigations have been undertaken on native oxide growth on silicon wafers [4,5] immersed in DI water with various dissolved oxygen levels and air (Figure 1); and on the benefits of functional H2 water on particle removal efficiency and hydrogen-terminating surfaces [6]. Degassing and regassing UPW can help meet new contamination criteria. Integrating this with a dHF cleaning process has a dramatic effect on its capabilities. HF last wet cleaning processes, single and two step, have been patented [7, 8], which provide a pristine and stable H-terminated silicon surface with an extensive queue time accommodated in various wet processing equipment. Some of the key components to making this novel technology work are:

  • specific dHF chemistry and process conditions;
  • ultra-degassed water (<100ppt);
  • H2 functional water or anionic surfactant [9] to achieve >90% particle removal efficiency);
  • insitu-rinse [10,11];
  • process equipment with high purity components and plumbing.

Description

SiOx Thickness(Å)

SiOx Monolayers 

SIMS AOD (atom/cm2)

SiOx/SiHx coverage (%)

Reference oxide layers

1

3.5

0.29

1.0

2.10E+14

7.20E+14

29/71

100/0

Typical native oxide

7

2.0

1.50E+15

100/0

Detection limit of XPS

0.1

0.029

2.10E+13

2.9/97.1

POR HF last wet clean

0.014

0.004

3.00E+12

0.4/99.6

Detection limit of SIMS

0.0005

0.00014

1.00E+11

0.014/99.986

Generalize that the silicon wafer surface is terminated with only SiOx or SiHx species overlooking C, F, and N.

Figure 2. Simplified perspective to understanding the relationship of SiHx : SiOx terminations for different thickness units, measurement methods and dHF last wet cleans process capabilities.

XPS studies show that this process [7] can produce non-detectable oxide (<0.1A) for up to 3 days. Encapsulated SIMS is another extremely sensitive method to quantify the lack of C and O on the surface after the dHF process. The lack of oxygen and carbon for these two characterization methods indirectly indicates the degree of SiHx on the surface after the wet cleaning processes (Figure 2). Depending on the DO of the UPW, this process can yield aerial oxide densities <3E12 at/cm2 (Figure 3). This capability has allowed for sub-800°C thermal budgeting for low-temperature Si and SiGe epi processes (Figure 4). This process has also proven to allow for a queue time in excess of 8 hours without the use of special handling between the clean and the epi process.

Figure 3. Encapsulated SIMS profiles for 650 no bake silicon caps on no clean and dHF etched with insitu rinse recipe with the degassed UPW’s dissolved O2 at 1.0 and 0.1 ppb processed wafers. The aerial oxide densities are 7.267E15, 2.078E13 and 2.627E12 atoms/cm2, respectively.

There is evidence that dHF is very effective at removing organic residues — like BHT and DBP — that outgas from plastic wafer shipping/storage boxes [12]. It also is especially good at removing oxidized polymers following plasma etch processes. In many, if not most cases, it is now possible that a single step dHF wet process can minimize silicon loss and lower COO and environmental issues.

To address the organic residue issue with IPA for wafer drying, enhancing less-effective methods like conventional spin rinse drying (SRD) could be an acceptable option to replace the existing process of record IPA drying technologies. Methods are under investigation. Two enhancements to a SRD tool that could allow SRD to resurface as effective drying tools include complementing the drying step with vacuum to reduce water micro-droplets and using low DO (degassed) UPW for the rinse to eliminate water marks [13]. The reduction of micro-droplets and watermarks could enable an equivalent drying capability to IPA-based dryers without the drawbacks of organic residues.

A brief, low-temperature treatment could be used to remove IPA residues and airborne organic contaminants that accumulate on the wafer surface between wet cleaning and the subsequent FEOL or BEOL process. It has been demonstrated that a 300° to 400°C bake via IR lamp heating for less than 2 minutes in an oxidizing environment effectively removes both organic contamination types [14]. A method has been developed that combines vacuum and IR lamp heating to ensure the most effective decomposition and desorption of the organic species and moisture.

Figure 4. SIMS profile demonstrating no detectable oxide (O) or carbon (C) with POR HF last clean (DO<0.1ppb) + 725C-80T-60s bake and 650C Si cap.

Conclusion

Although complex issues arise with tightening surface preparation specifications for emerging device technologies, solutions can be simple in nature. A single step dHF clean could accomplish overcoming the three identified hurdles associated with the new surface preparation criteria. Degassing the DO and the other dissolved species in UPW and chemicals has shown to be a valuable technique for dramatically reducing contamination levels in the cleaning, rinsing and drying steps of a wet cleaning process. SRDs could be enhanced for effective wafer drying, replacing IPA-based methods. Unavoidable airborne organic contamination and IPA drying residues can be nearly eliminated with a fast, reduced-pressure, low-temperature treatment. These simple approaches to achieve the challenging surface preparation criteria can be found on commercially available equipment.

References:
[1] K.A. Reinhardt and W. Kern, Handbook of Silicon Wafer Cleaning Technology 2nd Edition, pp29-32 (2008)
[2] The Ohmi Papers, Ultra-Pure Chemicals, published in Microcontamination-1990 edited by T. Chaney and R. Keeley, pp 80-82
[3] K. Motai, T. Itoga, and T. Irie, The Effect of Isopropyl Alcohol Adsorption on the Electrical Characteristics of Thin Oxide, Japan Journal Applied Physics, Vol. 37 (1998) pp.1137-1139
[4] M. Morita et al, Growth of Native Oxide on a Silicon Surface, J. Appl. Phys. 68 (3), 1 Aug 1990, pp 1272-1281
[5] F. Li, M. Balazs, and S. Anderson, Effects of Ambient and Dissolved Oxygen Concentration in Ultrapure Water on Initial Growth of Native Oxide on a Silicon (100) Surface, Journal of the Electrochemical Society, 152 (8) G669-G673 (2005)
[6] H. Morita, J. Ida, O. Ota, K. Tsukamoto and T. Ohmi, Particle Removal Mechanism in Hydrogenated Ultrapure Water with Megasonic Irradiation, Solid State Phenomena Vols. 76-77 (2001) pp. 245-250
[7] Stable, Oxide-Free Silicon Surface Preparation, US Patent 6,620,743 B2, Pagliaro Jr. et al. Sept 16, 2003
[8] Silicon Surface Preparation, US Patent 7,479,460 B2, Pagliaro Jr., Jan 20, 2009
[9] R. Vos, K. Xu, M. Lux, W. Fyen, R. Singh, Z. Chen, P. Mertens, Z. Hatcher and M. Heyns, Use of Surfactants for Improved Particle Performance of dHF-Based Cleaning Recipes, Solid State Phenomena Vols. 76-77 (2001) pp. 263-266
[10] P. Patruno, A. Fleury, H. Wyborn, E. Andre, and F. Tardif, HF Last Cleaning Before Silicon Epitaxy, unknown publication source, based on technical collaboration between SGS Thompson Microelectronics, CNET and LETI-CEA
[11] G. DiBello, S. Bay, C. McConnell, J. Parker (CFM Technologies Inc.), E. Chaney (Hewlett-Packard Co.) HF-Last Performance Using Direct-Displacement Wet Processing Technology Microcontamination Conference Proceedings 1994, pp. 538-547
[12] K. Saga and T. Hattori, Identification and Removal of Trace Organic Contamination on Silicon Wafers Stored in Plastic Boxes, J. Electrochemical Society, Vol. 143, No 10, Oct 1996
[13] K. Miya, T. Kishimoto and A.Izumi, Non-IPA Wafer Drying Technology for Single-Spin Wet Cleaning, Electrochemical Society Proceedings Volume 2003-26, pp. 57-63
[14] A. Daniel, et al., Dry Cleaning of Organic Contamination on Silicon Wafers Using Rapid Optical Surface Treatment, Solid State Phenomena Vols. 76-77 (2001) pp. 59-62

Robert Pagliaro received his BS in Physics from Thomas Edison State College (Trenton, NJ) and is Founder and President of RP Innovative Engineering Solutions, LLC; 6617 E. Saddleback Street, Mesa, Arizona 85215; ph.: 480-703-5054; web: www.teracleansolutions.com; email: rpagliaro1126@msn.com

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