September 8, 2010 – Accelerated capital spending, process technology roadmaps, and customer adoptions were among several key trends gleaned by Credit Suisse analyst Satya Kumar from GlobalFoundries’ recent technology conference.
– Capital expenditures accelerating. The company has pulled in spending plans over the past three months, and will increase capex again in 2011. (Good news for key suppliers ASML, Varian Semi. Equip. Assoc., and Lam Research.) GF says it represents nearly two-thirds of the total sub-65nm capacity expansion announced by all foundries — seen a hint of its plans to grab more marketshare in this area.
– 300mm, 200mm fab plans. 300mm capacity will be tripled over the next four years to ~270k WSPM, with 300mm/45nm/40nm capacity doubling in Fab 1 and Fab 7 by the end of 2010. Plans include: ramping Fab 1 in Dresden to 80k WSPM (300mm/45nm and below), pulling in NY fab expansion to complete shell and begin tool installs after mid-2011, with initial ramp to 60k WSPM (300mm/28nm and below); Fab 7 in Singapore ramping to 50k WSPM (300mm). The company has shipped ~210k wafers with 45nm process technology (immersion lithography, low-k BEOL).
GF currently has five 200mm fabs (Fabs 2, 3/5, 6, and 3E), all in Singapore, with ~176k WSPM capacity; plans are to expand to ~210k WSPM "over time." GF sees 18 foundries competing in 200mm; for its business it will target MEMS (leveraging transitions of 150mm to 200mm), IDM, and CMOS segments.
– Technology roadmap: Gate-first HKMG. The company "repeatedly emphasized the advantages of its gate-first high-k/metal gate choice as being better for scaling, easier design, better power/performance characteristics," Kumar writes. Benefits of gate-first HKMG, GF says, are 10%-20% die size and $75M cost advantage over a four-year lifecycle for advanced chips.
This presents a problem for customers who want to second-source their chip work, Kumar notes. While GF as well as partner Samsung both offer gate-first HKMG, leading foundry TSMC uses gate-last HKMG, which has very different process implementations — meaning the same part is likely not dual-sourceable. "Share gains if any are made at the 32nm nodes and below could be stickier in the foundry industry," he notes.
– Technology roadmap: Lithography. GF emphasized its work with immersion lithography, and EUV is "squarely" on its roadmap, with a first tool to be obtained in late 2012 (skipping a preproduction tool, thanks to its collaborative work with SEMATECH and U. Albany partners). (Kumar points out that customer STMicroelectronics now has an immersion scanner and plans to bring in an EUV tool by 2013.)
– Technology roadmaps: Packaging. With packaging/test making up 50% of the cost of finished goods, further innovations are needed: e.g. stacked dies, Cu wires and pillars. GF’s backend-of-line (BEOL) roadmap for 32nm/28nm (2009-2010) and 22nm/20nm (2011) shows lead-free Cu pillar technology, and three phases of 3D stacking: silicon interposer with processor and memory on the substrate, stacked die/through-silicon via (TSV), and high-volume manufacturing and TSVs.
For its BEOL capabilities, GF points to its bump/test facility in Dresden: ~40k wafers/month (300mm) capacity, high-lead and lead-free capacity (and Cu pillar in development), ~2.5 days bump cycle time, and a test floor for up to ~140 testers (take note, LTX-Credence/Teradyne/ATE/Verigy). It is also partnering with several subcons (ASE, Amkor, Stats/ChipPAC, and SPIL) for turnkey assembly/packaging.
– Customer activity. GF’s capacity expansion is notable in that its biggest customer, AMD, is squarely in the currently weak PC market. Nevertheless, AMD’s Fusion (Llano) chip, which combines CPU and GPU on one chip, is now ramping on 32nm process, with yields that GF would only describe as "not high at the moment," Kumar writes. GF is "hopeful" that it will win some of ATI’s GPU business, adding to work for big customers ST and Qualcomm, and is "aggressively" trying to become primary source for 28nm manufacturing.