by Dr. Philip Garrou, contributing editor
October 4, 2010 – The recent SEMICON Taiwan 3D Technology Forum (Sept. 9) shed some insight into what several foundries, assembly houses and customers are thinking about the timing for 3D interposers and full 3D IC.
Dr. Ho Ming Tong, GM and chief of R&D for ASE, commented that he expects the commercialization of interposers, what’s being called 2.5D, to arrive "in two years" and that interposers "will not be a simple transitional technology…[but will allow] the smooth transition from 40nm to 28nm." Concerning full 3D IC, he expects to see large-scale implementation "in three to five years." Others have interpreted these remarks as an indication that ASE has pushed back full 3D IC several years from their previously released roadmaps. After checking with ASE, it appears that the comments should not be taken as a slowdown in the ASE roadmap, but rather an indication of when 3D IC will be used in a widespread manner.
Kauppi Kujala, senior technology manager for Nokia, indicated that the company has been using devices with through-silicon vias (TSV) such as MEMS microphones and CMOS image sensors since 2006 and 2007, respectively. "For memory stacking, TSV can offer clear miniaturization opportunities and also [higher] performance and power reduction," he noted. He expects to see 3D silicon interposers "soon," driven mainly by low-k mechanical limitations. These will be single-chip packages, i.e., the chips will be bonded to a silicon interposer which will subsequently packaged in a standard package such as a BGA.
Kujala predicts wide-bandwidth memory on logic 3D IC stacks will be available 2012-2013, noting that "costs will be critical and standards still need to be put in place." Nokia’s first target for a wide IO package will be a package with four DRAM chips, targeting high-end smartphones and later migrating to mid-segment and lower-category phones. Nokia expects wide IO standards will be ready in late 2011.
Qualcomm’s Nick Yu, VP of engineering, also sees smart phones driving their interest in 3D IC. Yu emphasized that increased activity in standards is needed to mitigate risk and simplify the supply chain.
Shan-Chieh Chien, VP of advanced technology development at UMC, called 3D stacking with TSV the "big elephant" technology for foundries. UMC, which recently announced an alliance with Elpida and Powertech, commented that logic + wide IO DRAM stacking will occur in 2011-2012 consistent with the comments of Nokia and others. UMC also sees a significant future for silicon interposers with and without integrated passive components.
Carl Chen of Siliconware’s R&D group emphasized SPIL’s interposer 2.5D solutions, and showed their roadmap which calls for interposers late this year and memory stacking in 2011-2012:
|TSV technology roadmap. (Source: SPIL)|
A compilation of recent roadmaps from these and other major players shows a consensus on the commercialization timing expected for 3D IC.
Dr. Phil Garrou is a contributing editor for Solid State Technology and Advanced Packaging, and a frequent blogger with his Insights from the Leading Edge.