RAM-memory-research-A-RAM-RERAM-MSDRAM-MELRAM projects

(October 27, 2010) — The barriers and potential for voltage and density scaling of different memory devices beyond the 22nm is one of hot topics for current memory R&D. While speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.

RE-RAM researchers include Marie-Paule Besland and Laurent Cario from IMN (Institut des Matériaux Jean Rouxel CNRS). RE-RAM is a based on a new family of compound. Non-volatile reversible electric-pulse-induced resistive switching were indeed recently uncovered on AM4X8 (A = Ga, Ge ; M = V, Nb, Mo, Ta ; X = S, Se) single crystals at the IMN (Institut des Matériaux Jean Rouxel CNRS). In these chalcogenide compounds, 500ns voltage pulses (<10kV/cm) applied at Room temperature on a simple MIM device (Metal/AM4X8/Metal), yielding a non-volatile resistive switching between a high and a low resistance state. This effect was also demonstrated on GaV4S8 polycrystalline thin films that exhibit a reversible resistive switching at room temperature with writing/erasing times lower than 10µs and ΔR/R values higher than 25%. The resistive switching observed in the AM4X8 system corresponds neither to a phase change nor to any of the phenomena (thermal, electronic injection or ionic diffusion) proposed so far to explain the resistive switching effect in materials envisioned for RE-RAM applications. This memory based on Mott transition insulators offers Write Time (Twr) to 10µs at 1V, Access Time (Tacc) to <50ns at 0.4V and retention time > 1 year. Current density in write operation is better than the best RRAM solution (<3.103 A.cm-2).

A-RAM is a new type of capacitor-less 1T-DRAM. This memory introduces a totally novel 1T-DRAM device based on the coupling of majority and minority carriers in highly-scaled Fully Depleted SOI transistors (FD-SOI), but also compatible with bulk substrates. A-RAM is compatible with single-gate SOI, double-gate, FinFETs and multiple-gate FETs (MuFETs) and is believed a promising candidate for scaled memory applications. The team, A-RAM researchers Francisco Gamiz, Noel Rodriguez and Sorin Cristoloveanu, have developed an absolute original concept of architecture/design/operation which enables the physical separation of majority and minority carriers. Easy to control, State ‘1’ is defined by the presence of majority carriers which leads, via electrostatic coupling, to the formation of a minority carrier channel. State ’0’ corresponds to the absence of such a channel. Deep scaling compatible, the strengths of the A-RAM memory are: single-gate operation (no mandatory need for back gate biasing), high read margin (over a factor of 100) and low power consumption. In addition, A-RAM can be combined with double/multiple-gate FETs, introducing a new paradigm in DRAM technology: multiple bit memory in a single transistor. The A-RAM architecture has been developed in collaboration between the University of Granada (Spain) and the IMEP-LAHC laboratory (Grenoble, France).

MS-DRAM is an innovative memory cell based on the Meta-Stable Dip (MSD) effect. Meta-Stable DRAM was developed at the UCL and investigated in collaboration with the IMEP CNRS laboratory (INPG, France). Current CNRS researchers include Maryline Bawedin and Sorin Cristoloveanu. The MSDRAM is dedicated to multiple-gate SOI technology. MSDRAM takes advantage of the double-gate operation in fully depleted SOI. One gate is used to adjust the body potential and the other gate reads the corresponding current values in ‘0’ and ‘1’ states. The MSDRAM displays improved performances such as the retention time and Ioff current level. Furthermore, with this specific memory array configuration and operation, the programming time and voltage are competitive leading to significant reduction in power consumption. This device is aggressively scalable as demonstrated by numerical simulations down to 30nm gate length. In comparison with other memories using only one transistor, the MSDRAM exploits the full depletion and double-gate action (for enhanced scaling capability). This results in very long retention time up to 20sec at room temperature, high Ion/Ioff (103 with I1=20μA/μm and I0=10nA/μm), and low-power consumption.

The International laboratory LEMAC, part of the IEMN (UMR CNRS 8520), led by Nicolas Tiercelin, proposed a concept for a non-volatile magneto-electric memory, or MELRAM, based on the effect of an anisotropic piezoelectric stress on the magnetization of a giant magnetostrictive material embedded in a piezoelectric matrix (patent pending). Thanks to an internal biasing field, the magnetization of the magnetic element has two quasi-perpendicular equilibrium states. A positive voltage across surrounding electrodes leads for instance to a positive stress that sets the magnetization to one of the two states, and a negative voltage sets the magnetization in the other position, regardless of the previous state. For 100nm cell sizes, less than 1V is required to write the information. The writing current should be as low as in the ferroelectric memories, as well as the switching time. The readout can be made via spin-valve or GMR effects, which avoids destruction of stored information. This element could be used for RAM, non-volatile storage as well as in FPGA types components. Given the low energy consumption, this type of memory is a serious contender for 3D integration of memory cells, allowing a dramatic increase of the memory density.

The use of these emerging technologies will change chip design. Non-volatile memories such as magnetic random access memories (MRAMs) will help to overcome the drawbacks of classical programmable logic (as FPGAs) without significant speed penalties. Beyond the obvious advantage of power saving during the standby mode, it also will benefit the configuration time since there is no need to load the configuration data from an external non-volatile memory. Furthermore, during circuit operation, the magnetic tunnelling junction (MTJ) can be written, which allows a dynamic configuration and further increases the flexibility. Instant on/off power is the most important feature allowed by this kind of technology, suitable for many embedded systems from processor architecture to application specific integrated circuits (ASICs). LIRMM laboratory, under Lionel Torres, is currently working on emerging memories applications.

To become involved with any of these CNRS research projects, contact FIST SA, which is responsible for the licensing and the transfer of technologies from CNRS to the commercial sector. Learn more at www.frinnov.fr, e-mail Jean-patrice.coste@fist.fr.

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