20nm fully depleted SOI process available via CEA-Leti and CMP

(October 1, 2010) — CEA-Leti and CMP (Circuits Multi Projets) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory multi project wafers (MPW) initiative based on fully depleted silicon on insulator (FDSOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

“This process will allow researchers and engineers to experiment with the benefits of SOI on an advanced technology node,” said Bernard Courtois, head of CMP.

“Leti has been assessing fully depleted SOI’s key advantages for low-power, high-performance applications with several industrial customers,” said Laurent Malier, CEO of CEA-Leti. “It is time now to enlarge the diffusion of the FDSOI technology enabling test cases on 20nm process and beyond.” CEA-Leti has been involved with FDSOI R&D for a number of years and has developed internally both an advanced high-K/metal gate FDSOI process and a number of specific design and simulation tools based on industry-standard design-flow packages. FDSOI technology presents key advantages over conventional bulk technology for future nodes. The electrostatic integrity of the transistors is ensured by the thinness of the body without the need for extra litho steps, like in the case of FinFETs, or of channel doping. The consequence is a planar technology that exhibits at the same time excellent short channel behavior and significant improvement of the variability as shown in a number of recent papers.

The basis of the technology offer will be CMOS transistors with an undoped channel and a silicon film thickness of 6nm; high-k/metal gate stack; single threshold voltage (Vth) n- and pMOSFET with balanced Vth of ±0.4V; associated design kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics; and design kit documentation

The first run is scheduled to be launched in September 2011. All details will be available on the CMP website.

CEA is a French research and technology public organisation, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies in order to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. For more information about Leti, please visit www.leti.fr.

CMP is a broker in ICs and MEMS for prototyping and low volume production. Circuits are fabricated for Universities, Research Laboratories and Industrial Companies. For more information, visit: http://cmp.imag.fr

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