3D ICs in the spotlight at IMAPS by Dr Phil Garrou, contributing editor November 11, 2010 – Under the leadership of newly inaugurated president Rajen Chanchani of Sandia National Labs (see sidebar below) and president-elect Voya Markovich of Endicott Interconnect, the International Microelectronics & Packaging Society (IMAPS) held its 43rd annual meeting last week in Raleigh, NC. Industry veteran Dave Seeger of IBM served as general chair and local Lord Corp. chemist Sara Paisner served as technical chair for the meeting. In an invited plenary lecture, Cree co-founder John Edmond made the strong case for the imminent proliferation of LED lighting. Another invitee, Rao Tummala, professor and director of the Georgia Tech Packaging Research Consortium (PRC), made the case for moving to glass and silicon 600mm panel production to lower the cost for 3D interposers for mechanically sensitive 32nm and below IC and 3D interposers. Dave Miller, president of DuPont’s electronics & communications division, focused his invited talk on the use of DuPont’s thick film materials for solar panel fabrication and made an argument for grid parity being within reach. Another invitee, Leo Linehan, global business director of advanced packaging technologies for Dow Chemical’s advanced electronic materials division, commented that materials companies need to look for "common demands and requirements" for new product development expenses to make sense. He discussed two new Dow products: a new low viscosity, high-speed capillary underfill (CUF) which uses <3μm filler and a new aqueous developable low-k dielectric (k = 2.85). Regarding 3D IC technology, Linehan thinks that "soon everyone will be using it," but since much of the driving force is low latency high-bandwidth memory access, ultimately 3D through-silicon vias (TSV) "will be paid for by the DRAM manufacturers." The global microelectronic conference trend of focus on 3D ICs certainly continued at IMAPS, with 4 technical sessions and a panel session. In the session "3D Interconnect Technologies in Research Triangle Park," practitioners from the region (Microelectronic Consultants of NC, RTI International, Ziptronix, and NC State U.) detailed their latest 3D-related work. Paul Enquist, CTO of Ziptronix, sees their direct bond oxide technology catching on with fabricators of backside illuminated CMOS image sensors. He also shared the first released cross-sections (below) of a 10μm pitch, 463,000 connection daisy-chain built with the Ziptronix DBI process with Cu filled TSV fully protected by barrier layers, and he reported a 99.999% yield on such structures. John Lannon, engineer at RTI, warned of electrical failures on 3D test vehicles bonded with Cu/Sn/Cu intermetallics: "The yield goes to zero after 96 hours standard autoclave testing," he asserted. Standard epoxy underfills do not seem to solve the problem, but he pointed to a silicon underfill that allows device survival through the autoclave testing. More work is needed, he noted, to completely understand this issue and all potential solutions. Rhett Davis, Professor of EE at NC State, showed 3D specific designs which achieved 65% power reduction and an 800% increase in memory bandwidth. 3D veteran Rozalia Beica of Applied Materials’ Semitool division updated the audience on the company’s 3D work, and the activities of the global EMC3D consortium (Applied is a member). A 3D line at Applied’s Maydan Technology Center has run >50 integrated demos, he said, and the company’s newer via fill processes show a 50% reduction in overburden and significantly purer copper, which results in significantly less Cu extrusion (Cu pumping) and micro voiding. A 3D panel session headed up by RPI Professor James Lu addressed the 3D commercial timeline. Phil Garrou from Microelectronic Consultants of NC — yours truly — commented that roadmaps of many companies (TSMC, UMC, Elpida, ASE, etc.) now appeared in sync and all point toward commercialization in the 2011-2012 timeframe. Urmi Ray, senior staff engineer from Qualcomm, commented that his company, a very public supporter of 3D IC technology, sees "two years out (2012)" as "about right". Klaus Hummler, senior principal engineer from SEMATECH, was a little more hesitant about timing, indicating that Nokia is pointing toward product introduction in 2013, "but we believe this will be a stretch." When asked about standards, Qualcomm’s Ray, herself involved in several standards initiatives, pleaded for more work on standards "now." And for fabless companies, such standards a "matter of survival," Hummler added. Chanchani takes the helm at IMAPS US At last weeks 43rd IMAPS annual meeting, Dr. Rajen Chanchani of Sandia National Labs took over as president of IMAPS. Founded in 1967 as ISHM (International Society for Hybrid Microelectronics), the society merged with the International Electronic and Packaging Society (IEPS) in 1996 to become IMAPS. Now with 23 North American chapters and 21 international chapters, IMAPS hosts a variety of technical workshops, conferences, and professional development courses throughout the year, and its IMAPS Foundation provides annual grants to students involved in electronic packaging disciplines. Chanchani has worked in many leading-edge technology areas, but his most influential work, many believe, was on the Sandia "mini-BGA" — widely acknowledged as the first wafer-level package. He received his PhD from the U. of Florida, and worked at AVX and AT&T Bell Labs prior to joining Sandia in 1990. He was made an IMAPS Fellow in 2004. IMAPS new president Rajen Chanchani (center) receives congratulations from past president Howard Imhof (left) and IMAPS executive director Michael O’Donoghue. Dr. Phil Garrou is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.