(November 17, 2010) — In his keynote address at the MEPTEC Semiconductor Packaging Roadmaps conference (9/10/10, Santa Clara, CA), Bill Bottoms, chairman of Third Millennium Test Solutions (3MTS), gave attendees a dose of reality as he summarized the predicament facing the industry as it pursues 3D ICs.
"Everything becomes more difficult at deep sub-micron," said Bottoms. "Deep sub-micron implies changes in every parameter and makes package functions of device protection, power delivery, and signaling into and out of the device more challenging." A few of the challenges facing the industry as it implements 3D ICs will be: 1) the need to control power and enhance performance, 2) dealing with transistors that wear out within an expected product’s lifetime, 3) the introduction of new sources of stress, 4) thermal density increases, 5) operating voltage decreases, etc.
In an interview with Debra Vogler, senior technical editor, Bottoms details some of the methods that will be needed to address the 3D IC conundrum (e.g., redundancy, continuous testing, dynamic self-repair, graceful degradation). He also takes listeners on a kind of "back to the future" discussion as many of the solutions that will be needed for 3D ICs, he observes, were used years ago in mainframe computers 20-30 years ago. "It’s not an issue of invention, but one of integration with what is already known," said Bottoms.
Another challenge with die stacking is the need to establish known-good die (KGD). The testing challenges will be tremendous. For example, Bottoms told attendees that no test equipment will handle the number of vectors (which can be close to a trillion) at a reasonable cost and no one has a probe solution for 17GHz.