(November 10, 2010) — Alan Huffman, research engineer and program manager at RTI International, presented a paper at IMAPS 2010 titled "On the origins, status, and future of flip-chip and wafer-level packaging." In a podcast interview with Debra Vogler, senior technical editor, Huffman discusses the advantages and disadvantages of flip-chip and wafer-level packaging (WLP), along with potential solutions.
|Example of a 3D integrated module (Source: RTI)|
Speaking on silicon interposers, Huffman discusses how they enable "a so-called 2.5D integration that many companies see as a stepping stone on the way to true chip-to-chip integration." He also observes that they may be used at the smaller IC nodes to protect fragile low-k dielectrics.
Improved electrical performance, higher interconnect density, and reduction of the package size are benefits of flip-chip packaging. However, main disadvantages include limitations on the die size that can be packaged and still maintain a reliable lifetime performance. Though underfills can help, they raise costs; increasing solder bump sizes will also help, but do so at the expense of lowering the interconnect density. A potential solution is a silicon interposer as a flip-chip mounting substrate. To tackle electromigration, copper pillar bumps are being used to improve electromigration reliability, and are gaining wide acceptance, according to Huffman, who details additional benefits from their use.
|Process sequence for fan-out packaging|
Fan-out wafer-level packaging (FOWLP) increases the surface area of a device, increasing the number of interconnects and enabling manufacturers to take advantage of die shrinks. STATS ChipPAC has announced high-volume manufacturing for this technology, and Huffman anticipates that other OSATs will follow with their own versions.