(November 29, 2010) — Nick Kepler, VP, program management at Globalfoundries and a presenter at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) described the company’s rationale for selecting the gate-first approach to HK+MG processing.
Kepler said that the gate-first approach enables the overall Vt tuning range – it’s well over 300mV — and the company has not experienced Vt pinning issues. He also noted that process knobs can be used to tune Vt to meet product requirements. Kepler also said that gate-first offers repeatable LVT and SLVT options.
Two primary considerations that Globalfoundries had with respect to selecting gate-first is that at 28nm, gate-first provides true scaling relative to 40nm. He noted that there is an up to 50% increase in speed and a 50% reduction in energy/switch. An additional benefit of gate-first is that it sustains 40nm layout style advantages (e.g., bi-directional poly, poly jogs, large capacitors). There is also 10-20% smaller die relative to 28nm using a gate-last approach. Kepler’s observations were in direct contrast to TSMC’s Di Ma, who explains here why TSMC chose gate-last approach.
Kepler told Debra Vogler, senior technical editor, that Globalfoundries will harness three key enablers of technology scaling: lithography, materials (new materials and their integration), and 3D packaging. Kepler said that Globalfoundries will bring EUV into production at the 20nm node. He notes that, initially, EUV is not an enabler of 20nm, which can be accomplished with immersion lithography, but the company views EUV lithography as a cost-reducing agent at 20nm. And using EUVL at 20nm will allow the company to get practice with the technology in advance of when it will truly be needed: below 20nm.