How strain can protect devices from ESD: IEDM Preview

by Laura Peters, contributing editor

IEDM Previews:
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University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
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IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

November 11, 2010 – A recent study shows that in many cases, the use of strain engineering has a positive impact on a device’s robustness to electrostatic discharge (ESD). At the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA), researchers from the U. of California (Santa Barbara), IMEC (Leuven, Belgium), and Infineon Technologies (Munich, Germany) will discuss the impact of strain on different ESD protection devices in bulk silicon and SOI.

In one example, the use of strain in bulk gated diodes can result in a 35% increase in failure voltage using the maximum human body model (HBM). A 20% increase in normalized failure current is possible with SOI-based gate-grounded NMOS devices. This study provides a more comprehensive understanding of ESD sensitivity to strain in nanoscale protection devices.

In bulk gated-diode protection devices (Figure 1), strain is applied using a tensile contact etch stop layer of 1.2GPa. ESD robustness is enhanced with increasing levels of strain because the main current is the forward-biased p-n junction current. The increase in electron mobility is the main mechanism through which strain affects the ESD performance. The researchers determined that the increase in the maximum failure voltage according to the HBM can be 20% to 35%.

Click to Enlarge
Figure 1: In a bulk gated diode, positive pulses are applied to the p+ anode while the n+ cathode is grounded and the gate is floating.

In SOI gate-grounded NMOS devices, enhancement of ~20% in failure current can be obtained due to strain engineering (Figure 2). In these devices, ESD protection is enhanced by a simultaneous increase in electron mobility and decrease in hole mobility by the parasitic bipolar transistor, which turns on at a lower voltage in a strained device.

Click to Enlarge
Figure 2:The average failure current is improved at all gate lengths in the SOI gate-grounded NMOS device.

The ESD robustness of bulk silicon gate-grounded NMOS devices, unlike their SOI counterparts, is little impacted by strain. The researchers also found the impact of strain on bulk gate-tied-high NMOS to be negligible due to a lower effective strain.

This study and others shows that strain will continue to play a significant role in optimizing devices for ESD robustness.

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