IBM-fine-pitch-substrate-bumping-skips-solder-paste-beyond-C4NP

(November 23, 2010) — IMAPS 2010 presenter Jae-Woong Nah, research staff member, Packaging Materials Technology, at IBM’s Thomas J. Watson Research Center, briefed ElectroIQ on his conference paper: "Mask and mask-less injection molded solder (IMS) technology for fine-pitch substrate bumping."

Figure 1. Mask IMS method for substrate bumping. SOURCE: IBM

The paper describes the researchers’ work to develop a new pre-solder bumping technology of injection-molded solder (IMS) for fine pitch organic substrates (Figure 1). “Four years ago, IBM introduced C4NP (C4 new process) as a low cost and environmentally friendly process for applying C4s to wafers that are in volume production at IBM," said Nah. IMS is a variation of C4NP for solder deposition on fine-pitch laminates. The manufacturing technology currently in use for bumping on organic substrates is the solder paste stencil printing method. "However, the paste printing method is difficult to extend to <150µm pitch because the flux volume in the solder paste is about 50%," observed Nah. "The flux bridging after stencil printing leads to pre-solder bump bridging after solder reflow, especially with decreasing pitch and/or increasing pre-solder volume."

In an interview with Debra Vogler, senior technical editor, Nah explained how the researchers injected 100% pure molten solder instead of solder paste with a reusable film mask for forming high-volume solder on fine-pitch substrates.

Listen to Nah’s technical discussion: Download (for iPod/iPhone) or Play Now  

"Since only molten pure solder is used instead of solder paste, this method can achieve higher volume solder bumps for a given pitch, and can be used for fine-pitch applications," said Nah. Over the last year, the researchers ran hundreds of singulated laminates through the process and had no solder bridging and no missing bumps. The group demonstrated 70µm height solder bumps above the solder resist on 150µm pitch substrates (4,500 areal arrays in an 11 × 15mm area); it also demonstrated 35µm height solder bumps on an 80µm pitch substrate (15,000 bumps in a 10 × 10mm area).

 

Figure 2. Mask-less IMS method for substrate bumping. SOURCE: IBM

"In addition to the mask IMS process, we developed a mask-less solder bumping process — direct injection of molten solder without a mask,” said Nah (Figure 2). "It is a very simple and reliable process with low cost compared to any other bumping method," said Nah. He explained that the height of the solder bump is smaller than the mask IMS process because it is limited by the solder resist opening volume. "We demonstrated a 15µm solder height over the solder resist by using the mask-less IMS process."

Nah told ElectroIQ about technical challenges that had to be overcome. Because molten solder has a viscosity similar to water and the organic substrate warps, it is important to prevent leakage between the tool head and the mask as well as between the mask and the substrate. “We used a compliant material on the bottom of the tool head and flexible film mask,” explained Nah. “The compliant material creates a sliding seal between the tool head and the film mask, and the flexible mask follows any non-flat contours on the substrate under the influence of the compressive force that is distributed by the compliant material.” Nah also notes that in the mask-less IMS process, the low friction compliant material is important because the solder resist surface is very rough compared to the film mask. "The mask-less process today is perfect for applications that don’t require large solder volumes — and at a significant cost saving."

Nah believes that the IMS method redefines the role of solder bumping on a substrate. "The IMS method can provide a very large solder volume on substrates and it can reduce the chip bump volume, and potentially eliminate the wafer bumping process," observes Nah. As a result, the decrease in bump volume on the chip reduces the total package cost. "In the case of Cu pillars, the decrease in the Cu pillar height can reduce the stress on back-end-of-line during the flip-chip assembly process, in addition to decreasing the Cu die bumping cost."

Nah told ElectroIQ that IBM is working with another company to commercialize the process and they will have tooling available for large size substrate by sometime next year. "You will see a prototype tool using IMS technology next year," said Nah.

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