by Laura Peters, contributing editor
November 1, 2010 – One of the main concerns with three-dimensional stacked chips is the potential impact of mechanical stresses on CMOS transistors. The mismatch in thermal expansion coefficient (TCE) between copper (16.7ppm/°C) through silicon vias (TSVs) and silicon (2.3ppm/°C) can adversely affect the performance of devices and circuits. Researchers from IMEC and its partners conducted a comprehensive analysis of the impact of mechanical stresses on digital and analog device performance for single TSVs and arrays of TSVs. When they report on their findings at the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA), they will show that the complex interaction of stress components makes it difficult to use simple design rules without sacrificing large areas of the layout.
The IMEC group used their 3DSIC via first baseline process, which includes high-k/metal gate (HKMG) CMOS and implements TSVs after the contact module. The TSVs are 40μm in height and 5.2μm in diameter with a TEOS/O3 liner and Ta barrier. They fabricated and modeled mechanical stress and its impact for a variety of TSV placement patterns and a different transistor sizes in order to determine robust design rules. The tools used included finite element modeling (FEM) of TSV properties including CTE, stress in copper as a function of temperature, creep behavior, etc. Micro-Raman spectroscopy was used to measure local stress and verify FEM results. Calculated stress is averaged within the transistor’s channel separately for each stress component and converted into carrier mobility using standard bulk silicon piezoresistance coefficients.
Analysis of n and p-type DAC circuits with TSVs at increasing distances (1.7 to 20.7μm) from 5 × 10μm2 FETs revealed changes in saturation drive current (Idsat) of >0.5% at <20μm. In other words, for these devices, the "keep out zone" is 20μm.
For smaller FETs, the impact on Idsat was greater. The first figure (left) shows test structures with a matrix of 40nm FETs arranged in different patterns. The second figure (right) shows the simulated, associated Idsat variation. Short-channel transistors are expected to exhibit an Idsat variation up to 9%. Further investigation showed the keep out zone can range from 20-200μm for analog devices, depending on the number of TSVs in the matrix, and from 6-20μm for digital devices. These are substantial areas of silicon to set aside for stress relief.
|Left: Matrix of 40nm TSVs arranged in different patterns. Right: The simulated variation in PMOS Idsat of the TSV patterns of Figure 1. (Source: IMEC)|