TSMC chooses gate-last on 28nm CMOS

(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond.

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Figure. Transistor architecture beyond HK+MG. SOURCE: TSMC

Looking ahead, Ma summarized the company’s efforts with respect to transistor architecture beyond HK+MG (Figure) in a podcast interview with Debra Vogler, senior technical editor. The company has been working on doing depositions in different sequences to enhance the HK+MG stack, making it more stable.

Listen to Di Ma’s talk: Download (for iPod/iPhone) or Play Now

He outlined the company’s five factors that drove its decision to select the gate-last approach: speed, power, reliability, manufacturability, and scalability. Ma said that it was important to have an optimized solution that took each of these five considerations into account. TSMC’s data indicates that a gate-last approach enables process knobs that keep device power consumption low.

And from a manufacturability standpoint, by using gate-last, all the thermal/high-temperature processes can be completed before depositing the HK+MG materials, which keeps the threshold voltage stable.

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