TSMC chooses gate-last on 28nm CMOS

(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond.

Click to Enlarge
Figure. Transistor architecture beyond HK+MG. SOURCE: TSMC

Looking ahead, Ma summarized the company’s efforts with respect to transistor architecture beyond HK+MG (Figure) in a podcast interview with Debra Vogler, senior technical editor. The company has been working on doing depositions in different sequences to enhance the HK+MG stack, making it more stable.

Listen to Di Ma’s talk: Download (for iPod/iPhone) or Play Now

He outlined the company’s five factors that drove its decision to select the gate-last approach: speed, power, reliability, manufacturability, and scalability. Ma said that it was important to have an optimized solution that took each of these five considerations into account. TSMC’s data indicates that a gate-last approach enables process knobs that keep device power consumption low.

And from a manufacturability standpoint, by using gate-last, all the thermal/high-temperature processes can be completed before depositing the HK+MG materials, which keeps the threshold voltage stable.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>



Edwards launches new Smart Thermal Management System at SEMICON Europa 2016
10/25/2016Smart TMS helps semiconductor, flat panel display and solar manufacturers improve their process performance and safety by red...
Tektronix introduces Keithley S540 power semiconductor test system
10/19/2016Tektronix, Inc., a worldwide provider of measurement solutions, today introduced the Keithley S540 Power Semiconductor Test System, a ...
Novel Wafer Analyzer for up to 300mm wafer using high speed Raman Imaging Technology
08/08/2016Nanophoton introduces RAMANdrive - a new Wafer Analyzer - for a wide range of applications at semiconductor market a...