(December 28, 2010) – The IEEE International Electron Devices Meeting (IEDM) 2010, which took place early in December in San Francisco, included papers on all aspects of advanced semiconductor manufacturing. Techcet’s Michael A. Fury reviews several papers he saw at IEDM covering Nobel-Prize-garnering nanomaterial graphene.

(Additional information can be found online at 2010 IEDM Technical Program, using paper numbers provided here as a guide. All figures are reproduced with permission of IEDM.)

9.6: In a late news paper, Y.Q. Wu of IBM Research described the RF performance of a short (70nm) channel graphene FET on SiC. With careful control to minimize the contact resistance to the graphene, a cutoff frequency of 170GHz was obtained at a drain voltage of 2.2V. With further optimization and use of a self-aligned gate structure, a cutoff of 350GHz is believed to be achievable at 90nm channel length.

Figure 1. SEM image of a finished RF device (a, b); schematic view of a top-gated RF graphene FET (c). Source: Paper 9.6

23.1: An invited paper on graphene-based fast electronics and optoelectronics was presented by P. Avouris at IBM Research. Wafer-scale graphene was fabricated by desorbing Si at 1450°C from the Si face of a SiC wafer. Devices were then fabricated on a single crystal terrace. Although graphene is a zero bandgap material, bandgap devices can be fabricated using dual- or multi-gate structures. A 240nm gate device fabricated on a single terrace showed an fT of 230GHz. Graphene’s properties suggest that photodetector applications are an appropriate fit. A fast photodetector using alternating Pd and Ti electrodes was shown to work well at 10Gb/sec.

Figure 2. Schematic and SEM of the multifinger, two-different metal graphene photodetector and its utilization to detect optical data streams at 19Gbit/s. Bottom: Open eye test indicating error-free detection of optical data at 10GBits/s. Source: Paper 23.1

23.2: I. Meric of Columbia U fabricated a graphene FET using h-BN (hexagonal) as the gate dielectric, which has a lattice mismatch to graphene of only 2% but a thermal conductivity 600× greater than SiO2. The device configured with a Cr/AuPd ohmic contact had a mobility of 10,700 cm2/Vsec and good saturation behavior at gate lengths of 3μm, 1μm and 0.5μm, but high contact resistance remains to be reduced.

Figure 3. Optical image of GFET (left); schematic of the back-gated device structure (right). Source: Paper 23.2

32.4: K. Majumdar of the Indian Institute of Science simulated a dual-gated device with doped semiconductor source & drain and a bilayer graphene (BLG) channel. The bandgap-free nature of graphene is overcome by inducing a bandgap with the dual gates. Objective of the modeling is to obtain complementary unipolar BLG FETs for logic devices. The simulated device characteristics compare well with state-of-the-art Si technology, with IOn /IOff >104 and a subthreshold slope of ~110mV/decade for a 20nm gate length.

Figure 4. (a) Schematic of a d with source (S) and drain (D). (b) Bandstructure of an unbiased infinite BLG film with zero bandgap. (c) Bandgap opening in a "Mexican hat" shape under applied external vertical field. (d) Typical experimental transfer characteristics of a metal S/D BLG FET with on-off ratio of ~100 at Vdd=1mV and T=295K. Source: Paper 32.4.

Michael A. Fury, Ph.D., is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail

Read Fury’s other observations from IEDM Day 1, Day 2 AM and PM, and Day 3.

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