IEDM Reflections, Day 2: Graphene, RRAM, MEMS, and Jedi circuit designs by Michael A. Fury, Techcet Group December 17, 2010 – The IEDM Technical Fields Awards Luncheon (Tues. 12/07/2010) honored eight individuals for their contributions to the field of electronic devices: Ghavam G. Shahidi of IBM Research, for SOI CMOS development; Bijan Davari of IBM Research, for submicron CMOS and STI development; Takehisha Yaegashi, Shoichi Sasaki, and Shinichi Abe, at the time all at Toyota Research, for development of the Toyota Hybrid System which became the Prius; John E. Kelly III of IBM Research, for management leadership & strategic vision; Mark J.W. Rodwell at UC Santa Barbara, for sub-millimeter wave InP HBTs; and Tsu-Jae King Liu at UC Berkeley, for development of the FinFET. Following the award presentations, James Clifford of Qualcomm CDMA Technologies talked about the evolution and directions for mobile wireless devices. We have already experienced a convergence of computers and consumer devices with wireless technology. Today we are making the full Internet experience available through wireless devices. More than half of the world’s inhabitants will have their first Internet experience with a wireless device rather than an Ethernet connection. One example of an emerging application that is driving new technology is digital band-aids that can notify a patient and the doctor of signs of infection. The new Mirasol display is an interferometric modulation device with near infinite pixel and color resolution at low power. Fabless Qualcomm shipped a record 7B chips in 2010. (Additional information can be found online at 2010 IEDM Technical Program. All figures are reproduced with permission of IEDM.) 23.1: An invited paper on graphene-based fast electronics and optoelectronics was presented by P. Avouris at IBM Research. Wafer-scale graphene was fabricated by desorbing Si at 1450°C from the Si face of a SiC wafer. Devices were then fabricated on a single crystal terrace. Although graphene is a zero bandgap material, bandgap devices can be fabricated using dual- or multi-gate structures. A 240nm gate device fabricated on a single terrace showed an fT of 230GHz. Graphene’s properties suggest that photodetector applications are an appropriate fit. A fast photodetector using alternating Pd and Ti electrodes was shown to work well at 10Gb/sec. Schematic and SEM of the multifinger, two-different metal graphene photodetector and its utilization to detect optical data streams at 19Gbit/s. Bottom: Open eye test indicating error-free detection of optical data at 10GBits/s. 23.2: I. Meric of Columbia U fabricated a graphene FET using h-BN (hexagonal) as the gate dielectric, which has a lattice mismatch to graphene of only 2% but a thermal conductivity 600× greater than SiO2. The device configured with a Cr/AuPd ohmic contact had a mobility of 10,700 cm2/Vsec and good saturation behavior at gate lengths of 3μm, 1μm and 0.5μm, but high contact resistance remains to be reduced. Optical image of GFET (left); schematic of the back-gated device structure (right). 18.3: Device leakage and RF channel switching are among the problems driving a reverse trend from electronic switching back to mechanical switching in the form of MEMS devices, as presented in an invited talk by Tsu-Jae King Liu of UC Berkeley. A MEMS air gap of 1nm can provide IOn/IOff ~ 1010. Planar plates are used as actuating elements rather than linear mechanical levers; a see-saw configuration guarantees that complementary logic functions can be satisfied. Devices have been shown to endure 1015 cycles, satisfying most wireless applications with a 10-year lifetime. MEMS logic functions can be fabricated with 2×-4× fewer devices than the corresponding CMOS functions. (a) 3D schematic of the see-saw relay structure and definition of design parameters. (b) Schematic cross-sections illustrating complementary operation. (c) SEM views of a fabricated see-saw relay. 17.4: It really didn’t matter what the subject matter was — there was no way I was going to miss an invited talk entitled "May the Fourth (terminal) Be With You: Circuit Design Beyond FinFET," by H. Kioke of AIST, Tsukuba. True to form, the opening slide began with large text receding upward at an angle and off into the darkness of space, just like Star Wars. His proposal is a 4-terminal device in which the single FinFET gate that surrounds three sides of the channel is split into separate two gates by removing the portion of the gate the crosses on top of the channel. In the fab this would be done by CMP; in his slide he used a light saber. The resulting Cross-Drive XMOS device operates with an input gate and a separate control gate, and falls into the More Than Moore category. Target applications for this low voltage, low leakage device include flex power FPGA, flex pass gate SRAM, and low voltage op amp. Development of a 4-terminal SPICE model is underway. 21.5: To satisfy the demand for NVRAM on flexible substrates, C.H. Cheng of National Tsing Hua U proposed a very high performance non-charge based resistive RAM using an ultralow-power hopping conduction mechanism. The RRAM device stack consisting of Ni/GeOx (8.5nm)/HfON(6nm)/TaN on a transparent PI film showed a mechanical endurance of 105 bending cycles, electrical endurance of 105 cycles at 50nsec switching that required 5μW power. Comparison of device data for various NVM devices on flexible organic substrates (PET, PI, PES) or rigid glass. 23.6: I returned once again back in the graphene session, where H. Wang of MIT presented a GHz ambipolar frequency multiplier based on CVD graphene. The test device fabricated had a cutoff f-3dB~1.5GHz. For hypothetical THz devices, the specs will need to be 250Ω · μm contact resistance, 40nm gate length with 5-10nm Al2O3 gate dielectric, and graphene mobility μ~2000-3000 cm2/Vsec. To achieve these goals, he proposes building the device circuitry in silicon with the contacts on top, then laying a PMMA-transferred graphene layer on top followed by graphene patterning and contact bonding. Such fabrication work remains to be done. Structure of the fabricated devices. Ohmic metal: 2.5nm Ti/ 45nm Pd/ 15nm Au. Gate dielectric: 5nm SiO2 (e-beam) + 15nm Al2O3 (ALD). Gate metal: 30nm Ni/ 200nm Au/ 50nm Ni. Source to drain distance LDS = 1.7μm. Gate length LG=1.6μm. Channel width W=25μm. Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail firstname.lastname@example.org.