Scaling-FinFets-Increase-fin-height-reduce-geometry-apply-strain

(December 22, 2010) — To prepare for the time when the semiconductor industry might choose FinFETs at advanced nodes, SEMATECH researchers investigated possible scalability paths. The results of their work was presented at IEDM 2010 (12/6-12/8/10, San Francisco, CA) in paper #34.2 ("Strained SiGe and Si FinFETs for high-performance logic with SiGe/Si stack on SOI"). In this, part of a series of podcast interviews with Raj Jammy, VP, materials & emerging technologies, SEMATECH, he explains the group’s rationale and results behind its work.

 Listen to Jammy speak at IEDM: Download (For iPod/iPhone users) or Play Now

Jammy told Debra Vogler, senior technical editor, ElectroIQ, that the intent of the work was to identify a possible scalability path for FinFETs, which are expected to be used by the industry within the next few generations. "Not only can we use SiGe to get the fin architecture working, but we can apply different approaches to get the SiGe in place," commented Jammy. The group also discovered that how the device is made also affects its performance.

Other IEDM interviews with Raj Jammy:
 
Advances in dielectric dipole-mitigated Schottky barrier height tuning
III-V MOSFET on 200mm Si fabbed using industry-standard tools: SEMATECH at IEDM

The group reported high-performance (Ion~1mA/µm at Ioff 100nA/µm at 1V Vcc) short-channel pFET SiGe/Si FinFETs as a result of a high SiGe mobility, low Tinv (scaled high-k) and low Rsd combined to uni-axial strain additivity (Fig. 1). The group concluded that SiGe/Si pMOS FinFETs outperform Si FinFETs (Fig. 2): SiGe/Si p-FinFET Idsat is 10% higher compared to Si fin device and a compressive stressor boosts SiGe/Si FinFET by an additional 23%.

Figure 1. Advantages of SiGe/Si FinFET pMOS. SOURCE: SEMATECH

"We’re not trying to predict when FinFETs will be introduced, but rather, when they are introduced, what would be the options from there to scale those technologies," Jammy said. Options include increasing the fin height, reducing geometries (to get better control in the channel and probably higher drive currents), applying strain, and applying high-mobility materials, said Jammy.

Figure 2. SiGe/Si FinFET outperforms Si FinFET. SOURCE: SEMATECH

Follow Solid State Technology on Twitter.com via editors Pete Singer, twitter.com/PetesTweetsPW and Debra Vogler, twitter.com/dvogler_PV_semi.

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