Which-transistor-path-FinFET-tri-gate-FDSOI-Ge/III-V-bulk-CMOS

(December 14, 2010) — At the IEEE International Electron Devices Meeting (IEDM 2010) held in December in San Francisco, much of the discussion — particularly at company-sponsored events — was about which transistor structures and materials would garner the most support at 16nm and below. In this podcast interview, Dean Freeman, VP of research, Gartner, provides his perspective on the various paths: FinFETS, tri-gates, fully-depleted SOI (FDSOI), Ge/III-V, bulk CMOS, and so on.

Listen to Freeman’s IEDM interview: Download (iPod/iPhone users) or Play Now

It is highly unlikely the industry will use planar CMOS, even with high-k/metal gates (HKMG), because of leakage, notes Freeman. He observes that FinFET technology is the furthest along at this time, but lithography will be a challenge, as will some of the doping.

Mobility will be the next challenge and Freeman speculates that the industry might use Ge in the gate sooner — even in 22/20nm planar technology — rather than FinFETS. But so far, everyone has been noncommittal on how and when to go vertical at this time.

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