by Dr. Phil Garrou, contributing editor
December 22, 2010 – Global 3D IC technology leaders recently assembled in Munich at the IEEE 3DIC Conference in Munich, with Peter Ramm (Fraunhofer EMFT Munich) and Eric Beyne (IMEC) as co-chairs.
Jeff Burns, director of VLSI systems at IBM/Yorktown Heights, offered the perspective that 3D IC technology "will require many changes to architecture, VLSI design, design IP, tools, technology, and manufacturing." In total, this promises to be much larger in scope than a CMOS technology generation — rather, "it will be similar to the transition from bipolar to CMOS," he said.
Ionut Radu, director of direct bonding technology at Soitec, revealed that standard damascene copper CMP does not provide the desired surface topography needed for a successful copper-copper bonding process due to Cu pad dishing and oxide erosion. Cu-Cu direct bonding, performed at room temperature under atmospheric pressure, requires flat surfaces with <1nm surface micro-roughness. Radu indicated development of a proprietary CMP process to limit the surface topography between the copper pads and the surrounding oxide dielectric. The special CMP surface preparation step leads to micro-roughness of both Cu and dielectric surfaces beings as low as 4-5Å.
Bonding of 5μm Cu pads has been successfully performed with a corresponding bonding energy of more than 1J/m2 obtained upon 200°C post bond anneal. The achieved bonding strength is reportedly sufficient to sustain post-processes such as silicon back thinning using coarse and fine grinding. Since no external force or pressure and temperature cycle is applied during bonding process, excellent alignment with minimum mechanical deformation is obtained.
Kiyoto Ito, researcher at Japan’s ASET (Association of Super-Advanced Electronic Technologies) described two 3D interconnection architectures — block and sandwich stacking — for stacked processor-memory LSIs. In the sandwich configuration, memory chips and processor chips are stacked alternately, and vertical interconnects in each PU-CHIP are divided into two groups: interconnects for global communications and interconnects for local 3D memory communications. Compared with block stacking configuration, sandwich stacking architecture shows 38% fewer vertical interconnects for the same throughput and reduces power consumption by 21%.
Dimitrios Velenis, design and cost expert at IMEC, discussed the impact of different manufacturing options on the cost of a 3D-stacked system. IMEC has developed a cost model based on its own 3D integration process flows to analyze and compare the cost effectiveness of different technology approaches.
When examining through-silicon via (TSV) processing cost vs. depth they find TSV depth affects the time for etching, liner and barrier deposition, and plating steps. TSV diameter and pitch affect the total area of a chip, the number of chips on a wafer — and eventually the cost of a 3D stack. Therefore, the cost of TSV processing increases with TSV depth and increasing aspect ratio.
Dean Malta, manager of Microfabrication Engineering at RTI International, shared his experiences on the fabrication of 3D TSV interposers by both TSV-first and TSV-last processes. In the backside TSV-last process, TSVs are formed after the front-side thin film processing is completed. Since these vias do not need to be filled, TSV reliability concerns due to Cu-Si CTE mismatch are reduced. Backside TSV processes must be compatible with the thermal limitations of the front-side thin film layers should they include polymer dielectrics.
The biggest challenge, Malta noted, occurs with making the interconnections between the TSVs and the front-side metal during bottom clear: "Too much etching can result in high TSV leakage currents, due to sidewall passivation loss, while too little etching can result in high resistance interfaces," he explained.
In the TSV-first process, the TSVs are etched as blind vias, from the front surface of the wafer. A significant advantage here is that the passivation "bottom clear" etch is not required as in the TSV last approach. Also, since there are no other materials on the wafer at the time the TSV are insulated and filled, high-temperature processes such as thermal oxidation can be used to produce high-quality oxide insulation. There is, however, concern over the copper-filled TSV CTE mismatch issues. Malta suggested a way to address these reliability concerns is to "limit the TSV diameter," but he added that for small-diameter TSVs "with an acceptable aspect ratio for processing, it may be necessary to thin the interposer wafer significantly." RTI studies were done with 100μm-diameter TSV with 6:1 AR, and TSV passivation was 2μm thermal oxide.
Malta also observed thermo-mechanical issues during backside BCB or PI RDL curing processes at temperatures of 250°C and 350°C, respectively. He believes the polymer delamination and cracking observed in the areas over the Cu-filled TSVs is due to copper protrusion during the dielectric cure. Separate tests at 400°C confirmed that the Cu in the TSV goes through a permanent expansion of 1.5-2μm during the 400°C exposure. In agreement with others in the industry, Malta found that these issues can be minimized by annealing Cu TSV at ~400°C after formation, and CMP of the resulting Cu protrusion.