22nm: The era of wafer bonding Technology forecasts for 22nm Addressing defectivity will require new surface-engineering processes at 22nm RoHS, device shrinks will continue to drive packaging technology Tooling and process technology vital for thin packages More collaboration is needed to improve process integration 22nm brings maskmakers, end users closer 22nm: The era of wafer bonding Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions A materials evolution and revolution for 22nm devices Enabling lithography for the 22nm node Keys to CMP and cleans: Defect reduction and process customization Gate structure/3D stacking "winners" will determine industry direction (This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.) Bioh Kim, director of business development for 3D and AP, EV Group, Tempe, Arizona, USA January 11, 2011 – With the leading edge of the semiconductor industry edging toward the 22nm production node, the "More Moore" debate rages on about the best lithographic solution to economically scale down to smaller design rules. Yet beyond "More Moore," an equally key trend looms large for IC manufacturers: "More than Moore," where the migration to the 22nm node involves not only scaling down, but building up — adding more heterogeneous device components, such as radio frequency (RF), power management, optics, and even MEMS devices, into a single package. In these complex systems-in-package (SiP), high-density interconnection is especially critical, which in turn is driving a greater emphasis on wafer bonding. Choosing the right bonding process depends upon several important criteria, including the thermal budget of materials properties and manufacturing processes, the alignment accuracy of the substrates, the throughput of the bonding process, and minimizing the risk of metal ion contamination. Based on these criteria, the two most viable bonding process methods for high-density interconnection are copper-copper thermo-compression bonding and a variation of silicon direct bonding, called plasma-activated low-temperature oxide bonding. Each has its trade-offs. Copper-copper thermo-compression bonding provides optimal alignment accuracy and electrical performance but is slower (typically 1-2 hours per wafer) and requires temperatures at the upper-limit of what is allowable for CMOS processing (around 400°C). Plasma-activated low-temperature oxide bonding, on the other hand, is initially a room temperature process and involves lower pressure — making it an easier and faster process (2-3 minutes per wafer). Subsequent annealing (at 200-400°C) as a batch process enhances the bond strength. However, it requires very stringent surface quality requirements and needs subsequent interconnection processes after bonding. In addition to adding more device components within a package at the 22nm node, chipmakers are also thinning the wafer (to ~50μm) to enable more stacked devices within the same package footprint. Since these thin wafers are extremely fragile, wafer bonding again plays a crucial role. By allowing device wafers to be temporarily bonded onto carrier substrates, they can undergo wafer thinning and through-silicon via (TSV) interconnection without risking damage. In temporary bonding and debonding, selecting the right material and bonding equipment vendors is critical. Many polymers are susceptible to deformity and bubbling at temperatures above 200°C, which impairs the quality of the bond. Leading materials companies are focusing significant resources to develop new polymers that are more stable at higher temperatures. In choosing the right wafer bonding process, chipmakers need to consider many criteria beyond which bonding process works best for them — including process expertise, optimization of equipment design to ensure stringent temperature, pressure and environmental control, and advanced wafer handling to ensure the integrity of these fragile and costly product wafers. In summary, the migration to the 22nm node is about more than just scaling down; it’s also about scaling up — with thinner devices and more of them stacked into a single package to enable increasing levels of functionality. These "More than Moore" trends require new manufacturing considerations — with wafer bonding playing a central role in each one.