Addressing defectivity will require new surface-engineering processes at 22nm Technology forecasts for 22nm Addressing defectivity will require new surface-engineering processes at 22nm RoHS, device shrinks will continue to drive packaging technology Tooling and process technology vital for thin packages More collaboration is needed to improve process integration 22nm brings maskmakers, end users closer 22nm: The era of wafer bonding Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions A materials evolution and revolution for 22nm devices Enabling lithography for the 22nm node Keys to CMP and cleans: Defect reduction and process customization Gate structure/3D stacking "winners" will determine industry direction (This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.) January 11, 2011 – The industry’s migration toward the 32nm and 22nm nodes will require development of new process integration schemes, device structures, new materials assemblies — and therefore, innovative surface-engineering solutions. No area of wafer processing will see a greater impact than surface conditioning. Today’s gate-first or gate-last architectures are already posing challenges to state-of-the-art surface-conditioning techniques, and the advent of a new generation of extremely thin films, high aspect ratios, and sensitive novel materials will require re-engineering of many traditional methods. Research centers such as imec in Belgium foresee new device structures and high-mobility channel materials based on Ge and III-IV compounds on silicon wafers, including some monolayer films. Such assemblies could meet the power and performance specifications of future CMOS nodes. But there are fundamental questions about whether current cleaning techniques will be equal to the surface-interface requirements at the 22nm node. Forming well-passivated interfaces will be key, but thermal budgets will likely prevent current surface treatments from being used. Conventional wet-process technologies may also be incompatible with the requisite new materials. Conventional plasma systems are already running into issues at the 45nm node using standard SiON/poly gate, which is known to cause corrosion and defectivity issues. Addressing these challenges will be extremely critical for high-k metal gate stacks, calling into question the existing FEOL photoresist dry-stripping technologies. Both the 32nm and 22nm nodes will require efficient nanoparticle removal without pattern damage or loss of materials, and only low oxidation of Si and exposed metal. Meanwhile, new wet chemicals like solvents, used in the past only for BEOL, will be introduced along with new dry-processing technologies. Issues with cross-contamination and environmental control will also play a major role in the design of new wafer-handling and storage strategies. Chipmakers will have to address both contamination prevention and elimination at the molecular level. These challenges likely will spawn a number of potential solutions and the best will compete on process quality and cost-of-ownership. Environmental impact will also be part of the equation.