This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.
Nick Pugliano, Marketing Director, Advanced Patterning Technologies, Dow Electronic Materials, Marlborough, MA, USA
January 11, 2011 — Though single-exposure patterning schemes are unable to meet 22nm specifications, advanced patterning technologies using ArF immersion allow us to continue shrinking critical dimensions in semiconductor devices. However, the use of ArF immersion at 22nm requires multi-step patterning processes and elaborate pitch-doubling schemes such as litho-etch-litho-etch (LELE) and self-aligned double-patterning (SADP) technologies. Although these technologies are more costly than any single-exposure process, they persist as a standard patterning solution for today’s 22nm device architectures in the absence of viable alternatives.
Yet the 22nm node also represents an inflection point, because additional shrink strategies will require further multiplication of these technologies. For example, quadruple-patterning is needed to extend these techniques beyond 22nm, but a simple multiplication of double-patterning would be costly and extremely difficult to deploy in mass production. The semiconductor industry is keenly aware that a single-exposure solution such as EUV will not be ready for 22nm due to its own set of challenges. Thus, the 22nm node has emerged as a proving ground for various innovative patterning processes geared toward on-track, low cost of ownership technologies.
Many approaches for printing critical contacts are currently under development and expect to see wide adoption at the 22nm node and beyond. Some approaches use shrink processes in new ways, but are not promising when printing the highest density patterns. Others explore tone reversal technologies that capitalize on improvements in aerial image contrast for certain feature types when using a negative, rather than positive, tone mask. Resist freezing via a track-applied, surface-curing solution or a high-temperature thermal curing step continues to be developed with the hope of reducing the number of vacuum-based CVD or etch steps, but these technologies still suffer from pattern fidelity issues and are not yet ready to displace SADP or LELE schemes.
For all immersion patterning processes, top coat use has been mainstream; however, top-coat-free technologies have been proven in foundry and memory applications. These technologies use self stratifying, surface active ingredients that control the properties of a photoresist to enable high scan speed immersion patterning, while simultaneously serving as an immersion barrier layer. On-track technologies utilizing spin-on silicon hard masks will extend as a way of lowering back-end processing costs. Finally, the use of spin-on anti-reflection coatings with precisely tuned optical properties will be important for the most critical layers, as these are needed to work in tandem with the underlying device stack to suppress back-reflected radiation from the large range of off-axis light that is present in high-NA imaging systems.
These approaches highlight the critical role that track applied materials have in enabling next-generation approaches to cost-effective patterning — a trend that is expected to continue as the semiconductor industry attempts to follow its shrink trajectory toward 22nm and beyond.