This is an online exclusive essay in SST’s Forecast for 2011: Back to Reality series.
Paul Kirby, Senior Product Manager, FEI, Hillsboro, OR USA
January 11, 2011 — Detailed analysis of structures on 22nm semiconductor devices is pushing the boundaries of conventional scanning electron microscope (SEM) technology. Even though equipment manufacturers continue to enhance the resolution of SEM-based tools, more and more failure analysis (FA) work is being conducted on transmission or scanning transmission (S/TEM)-based systems. TEM-based techniques offer the imaging resolution and analytical capability to take the industry well beyond 22 or even 15nm. To accomplish this, however, requires very thin sections to isolate the structure of interest. These sub-20nm-thick sections must contain the region of interest and require the ability to stop the thinning process at exactly the right time to capture what is frequently a one-of-a-kind defect.
At the 22nm technology node, we are seeing a shift to complex 3D device structures, such as FinFETS, that give more efficient control of the switching process by wrapping the gate electrode around the switched channel. This type of design necessitates even more precise end-pointing and sample preparation. These 22nm structures give us an insight into future transistor designs, where simple, 2D SEM cross section or S/TEM projection may not be able to reveal all of the important detail. It is possible to envision a future where 3D analysis techniques, such as electron tomography and slice-and-view reconstruction, could play increasingly important roles.
These complex structures are incorporating new materials that pose sophisticated analytical challenges. The challenge is made more difficult by sample thinness, which reduces the interaction volume and the strength of the Xray signal typically used for analysis. Advanced detector designs that collect more of the available signal have yielded tremendous gains in analytical speed and precision. These new materials are also driving a move to lower accelerating voltages that reduce damage to the sample.
Finally, we are experiencing a convergence to 3D packaging that involves combining many high-value chips together with advanced interconnect technologies, such as through-silicon vias (TSVs). The cost of failure is magnified by the fact that a failure in any one chip scraps the whole stack of very expensive, perfectly good die. This packaging FA problem lies at the other end of the size scale from wafer-based FA, since the analysis requires the rapid removal of relatively large amounts of overlying material without destroying the information contained in the failure. Plasma-based ion sources promise very high beam currents for fast milling, while preserving sufficient small spot (low current) performance to provide good imaging.
The ultimate challenge is to provide solutions to these problems that still meet the budget constraints of device manufacturers. Since the instrumentation is inherently more expensive — TEMs for imaging and analysis, and DualBeam (FIB/SEM) systems for sample preparation — the best solution lies in higher throughput that amortizes the cost over more samples. Equally important is reducing time-to-data to facilitate faster corrective action. These considerations all argue against more complex instrumentation and in favor of dedicated turnkey solutions that are faster and easier to use.