Materials forecast for 22nm devices Technology forecasts for 22nm Addressing defectivity will require new surface-engineering processes at 22nm RoHS, device shrinks will continue to drive packaging technology Tooling and process technology vital for thin packages More collaboration is needed to improve process integration 22nm brings maskmakers, end users closer 22nm: The era of wafer bonding Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions A materials evolution and revolution for 22nm devices Enabling lithography for the 22nm node Keys to CMP and cleans: Defect reduction and process customization Gate structure/3D stacking "winners" will determine industry direction This is an online exclusive essay in SST’s Forecast for 2011: Back to Reality series. Weimin Li, Deposition Director, Advanced Technology Development, ATMI, Inc., Danbury, CT USA January 11, 2011 – At 22nm, semiconductor devices will go through numerous changes, ranging from increased immersion double patterning lithography use to exotic materials systems implementation for their critical electrical properties. In advanced memory, we expect evolutionary changes in DRAM that will enable the continued use of ZrO2-based DRAM capacitor dielectrics but will involve a shift from the traditional Al dopant to new materials that either increase the k value or reduce leakage. While changes to the dielectric system at 22nm are evolutionary, revolutionary changes may start in the electrode. There is a chance that TiCl4-based ALD TiN electrodes will be replaced with transition materials that offer a higher work function to better control leakage. While new material systems will enable the continuation of Moore’s Law, there are significant implementation challenges from materials and process points of view. Many new precursor candidates are in a solid phase and standard temperature and pressure (STP), and will require cost-effective and production-worthy solid delivery solutions. Moving beyond 22nm is the start of the revolution, as DRAM makers face replacing ZrO2-based dielectrics. After decades of research on SrTiO3-based (STO) dielectrics, is it finally time to make it reality? For optimal performance, the ratio of Sr-to-Ti in STO has to be precisely controlled, or risk significant performance compromises. Delivering the right ratio of Sr to Ti throughout a 3D capacitor structure with extreme aspect ratios — across hundreds of billions of structures per wafer and millions of wafers per year — is a significant challenge. Schemes to increase the process window, such as larger capacitor size or device integration changes, may increase DRAM’s overall cost at a time when reducing cost per bit is paramount. Similar to 22nm, the electrode is another factor that impacts the cost of ownership for STO. STO-based dielectrics will likely require noble metal electrodes such as Pt, Ir or Ru. Considering cost, Ru is the mostly likely candidate for DRAM capacitor electrodes beyond 22nm. Given the efficiency of the ALD process for Ru, two layers of 200Å electrodes will need approximately 2.5g of Ru precursor per wafer. Assuming the cost of Ru is reduced by an order of magnitude, Ru-based electrodes would still be two orders of magnitude more expensive that traditional TiN electrodes. Going to 22nm will involve evolutionary changes to the DRAM capacitor, but beyond 22nm will require more revolutionary changes: make STO/Ru technology production-worthy at high volumes, and maintain reducing cost-per-bit by making it cost-effective. It will be interesting to monitor how the semiconductor industry addresses these challenges in an “acceptable to all” manner.