More collaboration is needed to improve process integration (This is an online exclusive essay in SST‘s Forecast for 2011: Back to reality series.) David Hemker, Ph.D., VP, new product development, Lam Research Corp., Fremont, CA USA January 11, 2011 – As we look ahead to the 22nm technology node and beyond, it is no surprise that the smaller feature sizes required will further exacerbate many of the process integration challenges Technology forecasts for 22nm Addressing defectivity will require new surface-engineering processes at 22nm RoHS, device shrinks will continue to drive packaging technology Tooling and process technology vital for thin packages More collaboration is needed to improve process integration 22nm brings maskmakers, end users closer 22nm: The era of wafer bonding Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions A materials evolution and revolution for 22nm devices Enabling lithography for the 22nm node Keys to CMP and cleans: Defect reduction and process customization Gate structure/3D stacking "winners" will determine industry direction already present today. Although there are no obvious disruptive changes with this next generation, the ongoing evolution of device technology involves increasingly complex multi-layered structures. As the number of layers continues to grow, device architectures are becoming more sensitive to the interactions of film interfaces. This dynamic is beginning to have significant influence on process integration. To address this emerging challenge, equipment suppliers will need to develop a greater awareness of sequential processes and related integration issues to provide effective solutions. As a result, we expect to see more collaboration between suppliers and chip manufacturers to accelerate problem solving. Equipment suppliers now have an opportunity to play a more significant role in helping manufacturers. The complex challenges of advanced high-k/metal gate structures serve to illustrate suppliers’ potential contributions. Here, multiple process steps from deposition to clean are involved in forming several very different layers of the transistor structure. Successful process integration requires effectively managing the interface properties of the films since these can have an effect on the subsequent process steps. To address integration challenges, suppliers will need to tailor their processes and equipment designs. It is not sufficient to focus solely on the primary unit process when designing next-generation equipment. Interactions with upstream and downstream steps must also be taken into account. This can extend to providing expertise that enables manufacturers to improve process results, adjusting processes to ease the integration of subsequent steps, or integrating processes. For example, we are leveraging our etch and clean process expertise and working closely with end users to provide solutions that support integration. For example, a clean step that follows a contact etch may be more readily optimized based on intimate knowledge or even adjustment of the etch chemistries. In another case, a new process was developed that combined etch, strip, and deposition chemistries in order to protect ultralow-k films during damascene etch, thereby reducing film damage and eliminating the need for additional repair steps. These examples illustrate how adjustments in one process can ease the difficulty of the next step, and we expect to see suppliers providing more compensatory capabilities on their products in support of integration. Those suppliers who demonstrate excellence in core capabilities and have a good understanding of related processes will be able to add significant value in supporting integration needs for next-generation devices. High-trust collaborative relationships with chip manufacturers will facilitate these activities and enable manufacturers to more quickly implement new technologies.