Tooling and process technology vital for thin packages Technology forecasts for 22nm Addressing defectivity will require new surface-engineering processes at 22nm RoHS, device shrinks will continue to drive packaging technology Tooling and process technology vital for thin packages More collaboration is needed to improve process integration 22nm brings maskmakers, end users closer 22nm: The era of wafer bonding Failure analysis challenges at 22nm drive the need for turn-key failure analysis solutions A materials evolution and revolution for 22nm devices Enabling lithography for the 22nm node Keys to CMP and cleans: Defect reduction and process customization Gate structure/3D stacking "winners" will determine industry direction (This is an online exclusive essay in SST‘s Forecast for 2011: Back to Reality series.) Dave Foggie, semicon & alternative applications manager, DEK, Weymouth UK January 11, 2011 – There appears to be one goal driving the market in both the wafer-level and substrate-level sectors: getting thin! This is no diet fad but a real challenge for manufacturers that is impacting the technology needed to compete. Lower Z-heights are a key target in wafer-level assembly. Thinner wafers — we see 75μm regularly and are expecting 50μm thicknesses any time soon — work with smaller ball diameters to reduce component profile height. Then there’s the increasing use of thinner coatings for die attach materials; we’re seeing these drop from typically 50μm to as thin as 25μm to give improved performance through better conductivity and shorter signal paths. Thinner and leaner are features of a growing array of emerging packaging technologies, such as fan-in and fan-out, where encapsulated die with multiple I/O offer huge net gains in functionality. Overall, these low-profile form factors are great news for the miniaturization demanded by end-user electronic products. But they have an impact on wafer bumping and ball placement, which is where manufacturers will need to exercise caution in otherwise proven and dependable processes. And what of substrate level? Here, getting thinner also seems to be the trend for packaging. Take thin core and coreless technologies for instance: essentially very thin and flexible substrates that present their own problems, such as warpage and dimple distortion. Imagine a conventional flip-chip assembly with passives, some silicon, and underside bumps; it will measure about 1mm thick. But these new package technologies are pushing that down to 0.2mm or less, which is desirable because again, being thin is great for miniaturization. One downside that presents a challenge for device handling and processing is the propensity for the thin structure to "dimple" as the underfill cures and distorts the thinned substrate material. That can make the device less than perfectly flat. This technology isn’t mainstream yet, but experimentation and feasibility studies are well underway and it shows the path for the future. My 2011 forecast is that innovative tooling and process technology will become paramount in addressing thinned packaging and ramping up to volume, reliably.