By Debra Vogler, senior technical editor
March 1, 2011 — At this week’s SPIE Advanced Lithography conference in San Jose, Debra Vogler, senior technical editor, caught up with Franklin Kalk, CTO of Toppan Photomasks, to get his input on how EUV lithography development is shaping up, comparing the pros and cons of EUV lithography vs. e-beam direct write (EBDW), and why there’s room for both technologies in leading-edge semiconductor manufacturing.
Listen to Kalk’s interview: Download (iPhone/iPod users) or Play Now
Between now and likely production-volume EUV in 2015-2016, we probably will have some surprises, Kalk notes. Some areas are fairly well mapped out already; mask patterning "is relatively ok," he said, noting incremental improvements in writing, CD control, and registration control. But the "qualification and finishing" side still needs a lot of work, e.g. in defect management, inspection, repair, repair verification, etc., where "things are a lot more open," he said. The infrastructure is not in place for doing actinic inspection or actinic repair verification — and "we don’t really yet have the blank optimized" for the absorber stack, he noted, which is the next level. "While we know what the multilayer stack is going to look like, we don’t really know yet what the absorber stack should be, or will be, and we don’t yet know what the backside coating will be," he said.
Regarding 193nm immersion masks and the change to multiple patterning, Kalk points out that this technology is pretty well-established, going back to complimentary PSM back in the days of KrF for logic, and also with KrF for memory to give needed pitch capabilities.
Both logic and memory need a bridge to EUV. But logic generally runs much lower run sizes (not all logic is MPUs), so cost-effective double-patterning is a challenge: it’s expensive, throughput is lower, and mask costs are higher.
This leads to a comparison of EUVL vs. an alternative: e-beam direct write, championed by TSMC’s Burn Lin. It’s hard to cost-justify EUV lithography on very low wafer volumes, Kalk notes, but EBDW’s lower throughput makes it a tough sell at even modest wafer volumes. Ultimately, he says, there’s a gray zone between the two — applications may require modest volume where EUV isn’t really cost-effective, but EBDW isn’t capable of the required throughputs.
And if the litho decision really depends on the application and cost considerations, will chipmakers (especially foundries) have to invest in both technologies and separate infrastructures, resists, training, support, etc.? The industry has been geared far more heavily toward EUV than its "deliberate" pace for EBDW, Kalk notes. "I think we’re going to have to see some stumbling, frankly, on EUV and some of the immersion technologies before we get more widespread adoption of EBDW," he says. "But, I think we do need it, especially for some of the lower-volume stuff. I’d hate to see that go away just because we don’t have a technology that can produce it cost-effectively."
More from SPIE Advanced Lithography 2011:
- Dr. Burn Lin of TSMC compares EUV and MEB
- Synopsys lithography verification in Proteus LRC handles EUV, double patterning
- SPIE keynote: Imec installs ASML pre-production EUV scanner NXE:3100
- Brewer Science launches immersion lithography products with OptiStack