Leveraging ion implant process characteristics to facilitate 22nm devices

Executive OverviewCertain inherent process characteristics such as precision, cleanliness, control and high productivity have been the hallmark of the entire implant industry for some time. Coupled with new capability, implant has become less of a commodity product and more enabling. In fact, the makers of the industry’s next-generation devices are looking to implant to improve established doping applications and facilitate new precision materials modification applications to provide device performance and yield improvements required for 22nm.

James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA

Recently, implant has re-emerged as an enabler improving device performance and process variability that would otherwise unacceptably degrade as technology moves to 22nm.

It is becoming more and more apparent that subsequent node transitions will expose new device performance and process limitations driven by scale and physics. Also, tool performance specifications that for several nodes have been taken for granted, will start to become obsolete. In particular, CMOS transistor yield is adversely affected by scaling due to increasing leakage current from multiple sources. The formation of highly activated ultra shallow junctions (USJ) that are both stable and abrupt is a significant challenge [1]. To circumvent this dynamic, the industry has developed damage engineering strategies through cryogenic implant technology and co-implants.

Other limitations are emerging that are impacting other process areas in the fab. Using implant as a precision material modification (PMM) tool, in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications to drive total available market (TAM) growth. For example, in the formation of ultra-sensitive gate regions, previously acceptable amounts of photoresist line edge roughness (LER) have become a source of threshold voltage variability that will increase leakage current and add to yield loss.

Cryogenic ion implant

A variety of complex device problems present themselves at the threshold of the 22nm technology node, particularly for boron-doped PMOS transistors. Dopant activation and defect creation at the sub-surface source/drain junction and surface regions become significant limiting issues. Through techniques referred to as damage engineering, implant is able to neutralize these effects and enable transition to 22nm.

Boron source/drain doping for PMOS transistors are run on high current ion implanters with beam powers that would normally elevate wafer temperatures that would cause photoresist masks to deform. Historically, simple backside liquid cooling schemes using commercially available chillers would be adequate to keep wafer temperatures from exceeding 70°C.

To facilitate low leakage, high quality sub-surface junctions, high dopant activation and low surface defectivity in the implanted region must be uniformly amorphous.

After milli-second flash or laser annealing, a low-defect, low-resistivity source/drain is desired. With device features at 22nm, junction depths must be under 10nm to minimize short channel effects (SCE). At these junction depths, natural dynamic annealing occurs during the implant process creating interstitial vacancy clusters at room temperature and above. By cooling the wafer during implant it has been demonstrated that self interstitials present at the end-of-range of the implant are reduced. This results in a significant reduction in dopant diffusion and deactivation. It has also been widely reported that lower temperatures down to -100ºC are the most effective [2]. With the expansion of cryogenic cooling into medium current applications such as HALO, maintaining wafer temperature during implant down to -100ºC will be absolutely essential.

Implementation of cryogenic wafer temperatures during implant at high vacuum present a rather significant engineering problem. Varian Semiconductor Equipment Associates (Varian) PTC II hardware has achieved the required temperature range while maintaining ultra-low particle performance and high productivity. Considering the added time necessary to cool and return the wafer to room temperature, Varian’s VIISta platform with batch load lock capability optimized this implementation for maximum productivity.

Molecular dopants

Another proven technique to enhance device performance and yield is through molecular dopants. For years BF2 has been used in the industry with excellent results. Recently the use of carborane (C2B10H12 – “CBH”) has proven an effective and stable option to introduce carbon into the lattice during PMOS source/drain doping.

CBH provides multiple benefits including reduction of end-of-range (EOR) defects, improving dopant activation and reducing lateral diffusion. A reduction of junction leakage (through diode leakage studies) of 50% has been reported [2]. The deactivation and eventual reactivation of boron in annealed silicon has been shown to benefit greatly from the use of cryogenic implant. Significant improvement in sheet resistivity when CBH is implanted at -100ºC compared to room temperature as illustrated in Fig. 1.

Figure 1. The best Rs/Xj performance has been shown @ -100°C implant temperature. The colder the better for Rs/Xj control.

Varian’s experience with Synopsis’ Technology Computer Aided Design (TCAD) Software has shown that increased surface activation of boron is due to ultra-shallow carbon associated with CBH [3].

Figure 2. Drive current and leakage current of PMOSFET with CBH.

Studies have shown that ultra shallow carborane implantation into pMOS S/D extensions provided enhanced surface activation and reduced sub-surface junction leakage [4]. When comparing the use of a pre-amorphization implant using Ge with and without CBH, the results were striking (Fig. 2). Drive currents of pMOS at -1.1V supply voltage increased by 20% with the use of CBH. Reduction of parasitic resistance and increased activation at the surface was responsible. Also, a demonstrated reduction in leakage current has been shown, which can be attributed to lower junction defectivity.

Tighter angle control

Prior to 32nm half-pitch, post-implant anneals would effectively smear out dopant profile variations resulting from “across wafer” or “across device” angle variations. Beam angle is affected by three prime components: 1) Global steering angle caused by beam tuning repeatability issues, 2) Local steering angle controlled by beam optics design, and 3) Within-device angle spread due to space charge effects [5]. It has been shown that for 32nm devices, as little as 1º of beam steering angle variation during extension implants can lead to a 3% reduction in Idsat [6].

To meet these angle accuracy demands, sophisticated beam angle measurement and adjustment technology has been developed that provides both vertical and horizontal control [7]. Current available technology has proven capability to control beam angle deviation down to 0.1% resulting in marked improvements to NMOS and PMOS Idsat.


It is generally accepted that uniformity and precision go hand in hand. Ultimately, control of non-uniformity will result from reducing variability in the implanter at various points in the beam-line. The effort to control variability will result in a cumulative set of added controls that ultimately increase an implanter’s flexibility for other applications. So it is with the current state of ion implant. Uniformity can be defined wafer-to-wafer, die-to-die and transistor-to-transistor. Micro-uniformity is of increasing importance as transistors get smaller and die get larger.

Precision dopant placement is affected by both ion beam dynamics and wafer handling capability. Controlling ion beams is particularly challenging since tool makers have to deal with space charge where the main challenge is transporting beams of like charged ions that naturally diverge. After years of development, ribbon beams have become a controllable means of beam transport. This development occurred at the beginning of the decade facilitating the move to single-wafer platforms. Also, wafer handling systems using highly flexible rotational platens that can reposition wafers without removal from the beam path provide exciting new capability with no loss in throughput. For example, implant can compensate for variability in other processes such as photolithography, chemical mechanical planarization, and spike anneal. Scanning an implant at different rotation angles creates a cross-wafer doping distribution that is intentionally non-uniform in opposition to the incoming non-uniformity from other process steps. This has been successfully implemented, particularly for improving threshold voltage variability on CMOS transistors, on medium current tools.

For the future, it is expected that enhanced uniformity control and beam angle control will contribute to new device integration efforts. As an example, device makers are looking to these technologies for development of 3D structures.

Energy contamination-free implant

Sub-2 keV implants are necessary to obtain the required ultrashallow junction (USJ) to control SCE for sub-45nm devices. These low energy beams lose more beam current due to space charge effects adversely affecting productivity. Instead of “drifting” these low energy beams, implanter makers have resorted to accelerating the beam, then decelerating it just before the wafer to maintain beam current and increase productivity. This deceleration creates neutralized ions that do not fully decelerate thereby entering the wafer at a higher energy. This energy contamination creates a tail on the profile that will increase leakage at the sub-surface junction. Recent improvements to high current beam lines have enabled full energy purity capability for deceleration technology applied to recipes from 500eV to 2keV.

Figure 3. Low-energy boron SIMS plot: The latest generation of high current implanters provide full energy purity at maximum throughput.

Since dopant activation is critical, device makers can now utilize phosphorous for NMOS source drain implants. Phosphorous has a higher activation level over arsenic. Historically, heavier arsenic was the dopant of choice because implanters ran more productively at higher energies and it diffused less during activation. Now device makers can run phosphorous at or below 2keV, achieving high activation while maintaining high productivity. Adding carbon co-implants to the NMOS source/drain region retards phosphorus diffusion during activation and keeps the junctions shallow. With this new implant technology, device makers can now achieve very high productivity free of energy contamination.

Improving lithography through materials modification

Implanting dopant atoms changes the conductivity of silicon. The use of implant with other materials results in physical or chemical changes to the target. Utilizing PMM with lithographic applications has resulted in several growth opportunities for implant. Reduction of line edge roughness (LER) or line width roughness (LWR) is one widely investigated application.

Figure 4. Comparison of implanted photoresist samples to a reference sample showing CD and LWR changes.

LER does not decrease as line-widths do. Consequently, it becomes a larger percentage of overall variability. Short wavelength LER and LWR is due to residual resist molecules left after development while long wavelength LER is due to interference patterns created by patterning light sources. LER for lithography typically uses heavy ions such as argon, neon or silicon which result in sputtering processes at the wafer when applied. Reduction or elimination of resist roughness through implant is enhanced by exploiting the angular dependence of sputter rates. In one study, silicon and argon were evaluated by implanting at a fixed dose of 5E15 ions/cm2 with a fixed tilt angle of 60 degrees [8]. In this analysis, both critical dimension and LWR were measured (Fig. 4). The ion implanted resist shows a change in CD as well as a reduction in LWR. At the same energy, argon still exhibits a greater CD loss and LWR reduction. As has been shown, non-reactive ion beam species has won out in comparative studies with other techniques providing anywhere from a 25% to 500% improvement [9].


Through a combination of established implant technology and newly developed hardware, ion implant is providing enabling applications for 22nm device integration. Cryogenic ion implant, where the wafer is held at temperatures down to -100C during implant, has proven to reduce device leakage and increase dopant activation. When used in conjunction with molecular dopants, such as carborane, where carbon can be introduced into PMOS source/drains, as much as a 50% reduction in junction leakage has been reported. Improvements in beam angle control have proven to increase device speed directly through improvements in Idsat. Tradeoffs between high productivity and low energy contamination have been prominent in the past. New hardware designs have attained the elusive goal of full energy purity and high productivity for the lowest energy implants. Finally, the use of implant for precision material modification has shown significant promise to extend other process capabilities namely in lithography through reduction of line edge roughness.


The author would like to thank Chris Campbell, Benjamin Colombeau, Fareen Khaja, Niranjan Khasgivale, Patrick Martin, Curt Norris, Tom Parrill and Dennis Rodier for their support.


  1. F. Khaja, B. Colombeau, T. Thanigaivelan, D. Ramappa, T. Henry, “Benefits of Damage Engineering for PMOS Junction Stability,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  2. C.I. Li, P. Kuo, H.H. Lai, K. Ma, R. Liu, H.H. Wu, et al., “Enabling Solutions for 28nm CMOS Advanced Junction Formation,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  3. C.I. Li, T.M. Shen, H.H. Lai, P. Kuo, R. Liu, H.Y. Wang, et al., ” Integration Benefits of Carborane Molecular Implant for State-of-the-Art 28nm Logic PFET Device Manufacturing,” IEEE Electronic Device Letters, to be published.
  4. B. Colombeau, T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura, H. Ito, “Ultra-Shallow Carborane Molecular Implant for 22nm Node p-MOSFET Performance Boost,” Inter. Workshop on Junction Tech., 2009, pp. 27-30.
  5. A. Renau, “Device Performance and Yield – A New Focus for Ion Implantation,” Inter. Workshop on Junction Tech, 2010, pp 1-6.
  6. H.J. Gossman, T. Romig, et al., “Precision Requirements for Advanced HP Logic Implantation,” Solid State Technology, July 2007.
  7. J.C. Olsen, et al., 17th Int. Conf on Ion Implantation Tech, Monterey, USA, pp. 129-132, 2008.
  8. P. Martin, L. Godet, A. Cheung, G. de Cock, C. Hatem, “Ion Implant Enabled 2X Lithography,” 2010 International Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
  9. C.R.M. Struck, R. Raju, M.J. Neumann, D.N. Ruzic, “Reducing LER Using a Grazing Incidence Ion Beam,” Proc. of SPIE Advanced Lithography 2009 Vol. 7273-49.


James L. Kawski received his BS in electrical engineering from The Rochester Institute of Technology and is manager of market research and communications at Varian Semiconductor Equipment Associates, 35 Dory Road, Gloucester Massachusetts, 01930; ph.: 978-282-2000; email james.kawski@vsea.com.

Solid State Technology | Volume 54 | Issue 3 | March 2011

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