Monthly Archives: March 2011

March 7, 2011 – Chip sales inched up in January from the previous month, according to the Semiconductor Industry Association (SIA), which foresees continued steady growth and proliferation, following a particularly strong year for chips in industrial and automotive sectors.

Worldwide sales of semiconductors (a three-month moving average) totaled $25.5B in January 2011, up 1.5% from December and 14% from a year ago. Sales growth was paced by the two biggest regions, the Americas (2.9%) and Asia-Pacific (2.7%), with Japan posting a -3.5% decline. Compared with a year ago, chip sales in the Americas are up nearly 25%, roughly double the pace (or more) of every other region.

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The rolling 3-mo. average, though, shows something of a decline, perhaps seasonal: -2.6% from the late 3Q period (Aug-Sept-Oct) to 4Q (Nov-Dec-Jan), with a sizeable dropoff in Japan (-8.8%), and other regions down slightly (-1% to -2%).

In a statement, SIA president Brian Toohey chose to reflect on 2010 successes rather than January numbers, highlighting the industry’s steady growth and widening semiconductor content in various products, "driven by strong demand across all major end markets as the products we use everyday become smarter, faster, and less expensive." Semiconductor sales rose ~32% in 2010, but were particularly brisk in industrial (50%) and automotive (44%) sectors, he noted. Integration of energy-efficient tools and increased automation, and emergence of hybrid and electric vehicles, entertainment, engine controls, and navigation systems spurred growth in those markets.

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March 7, 2011 — The Institute of Microelectronics (IME), an institute of the Agency for Science, Technology and Research (A*STAR), and electronic defense systems company ELTA Systems Ltd. (ELTA), a group and a wholly owned subsidiary of Israel Aerospace Industries (IAI), have inked an agreement to design and develop a novel through silicon via (TSV) substrate technology for multi-chip module (MCM) packaging.

The collaboration will result in new applications in multi-chip modules in radar, communication, and electronic warfare systems. The new technology platform would enable miniaturization of wireless applications that are faster, lighter and can withstand higher temperatures.
 
"Our joint goal is to develop innovative manufacturing and design processes to address the challenges associated with the use of TSV substrate technologies. We expect the resultant technology to have a fundamental impact on the defense systems industry, and on a wider scale, the worldwide semiconductor packaging market," said Professor Dim-Lee Kwong, executive director of IME. IME offers capabilities in IC packaging design and wafer-level molding.

By providing high density, very fine pitch interconnects and better stress tolerance between the die and substrate, TSV substrate technology is increasingly viewed as a critical means of resolving the growing geometric and material incompatibility between printed circuit boards and ICs. Apart from the greater miniaturization they afford, TSV substrate technology also offers more flexibility and shorter time-to-market. IME has been spearheading the development of this disruptive technology through its TSV research program and the 3D TSV consortium it leads.

The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR) in Singapore. Its key research areas are in integrated circuits design, advanced packaging, bioelectronics and medical devices, MEMS, nanoelectronics, and photonics. For more information, visit IME at http://www.ime.a-star.edu.sg. A*STAR is the lead agency for fostering world-class scientific research and talent for a vibrant knowledge-based and innovation-driven Singapore.

Israel Aerospace Industries Ltd. is a leader in the aerospace and defense industry and Israel’s largest industrial exporter. ELTA Systems Ltd., a group and wholly owned subsidiary of IAI, is one of Israel’s leading defense electronics companies specializing in intelligence, surveillance, target acquisition and reconnaissance (ISTAR); early warning command and control; homeland security (HLS); self-protection and self-defense, and fire control applications. Please visit www.iai.co.il for more information.

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by David K. Lam, Multibeam

March 7, 2011 – If anything in the litho world is certain, it’s that 193nm ArF immersion lithography (193i) is being extended. Nikon’s Masato Hamatani opened the Nikon LithoVision conference at this year’s SPIE Advanced Lithography symposium, describing concrete efforts in improving overlay to less than 2nm and throughput to 4000 wafers per day. While EUVL is delayed by challenges in light sources, resist, and inspection tools, Nikon is ready with 193i to support multiple patterning at 20nm half-pitch.

At the 1x node, Hamatani described a "complementary lithography" approach, a concept first introduced at last year’s LithoVision by Yan Borodovsky of Intel. "193nm immersion could work hand-in-hand with EUV or maskless lithography to enable advanced chip designs," stated Borodovsky then, showing a 20nm line/space pattern with 1D gridded layout that will benefit from EUV or EBDW for "line cuts" by avoiding quadruple patterning. In his SPIE 2011 talk, Hamatani assured the industry that it will be able to use a line-cutting approach — and concluded with an intriguing remark that, besides efforts in 193i and EUV, Nikon is "considering other potential game-changers."

The twin themes of 193i extendability and complementary lithography appeared throughout LithoVision. TEL’s Hidetami Yaegashi focused on 193i extendability, showing fascinating results in 193i pitch quadrupling, with line/space patterns at 25nm full pitch and hole patterns at 56nm pitch. In his estimation, at 22nm half-pitch, 193i with pitch division is lower-cost than EUV — even if EUV reaches a throughput of 150 wafers per hour.

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We saw a glimpse of Intel’s vision for the future in Dr. Sam Sivakumar’s presentation. He showed how Intel moved to 1-D design layouts at their 45nm node. The 1-D layout style (also known as unidirectional gridded layout) allowed Intel to use mature optical lithography tools, increasing process window and enabling a quick ramp. Because of the many benefits, Sivakumar stated that "Gridded layouts have now become ubiquitous — the way of the future."

Looking ahead to the 14nm and 10nm nodes, Sivakumar noted EUV is late. This brought Sivakumar to the theme of his talk: Intel’s design rules must remain compatible with optical multiple patterning and complementary lithography. Intel’s design teams must be flexible and able to react quickly to implement EUV or e-beam lithography, enabling the company to take advantage of the most cost-effective lithography solution available.


David K. Lam and founded Lam Research in 1980; currently he heads up the David Lam Group, an investment and advisory firm for high-tech companies, and also chairman of Multibeam Corp. Contact: davidlam.com.

March 7, 2011 — Alcatel-Lucent Bell Labs, Thales announced that CEA-Leti has joined the III-V Lab. The public-private partnership will combine III-V semiconductor and silicon technologies, opening up new research perspectives and dynamics targeting telecom, industrial control, environmental testing, defense, security, and space applications.

The enlarged III-V Lab will include more than 130 researchers, technicians, and doctoral candidates.

Partnering expertise in silicon, microelectronics and heterogeneous integration, the lab’s goals include:

  • The integration of speed, power and optical capabilities of III-V components on silicon CMOS integrated circuits (ICs);
  • Development of smarter, smaller components with innovative features by heterogeneously integrating active III-V components (optical, microwave, high-power components) with silicon circuits and microsystems;
  • The production of III-V components on silicon substrates and in silicon microelectronic manufacturing lines to reduce costs.

Established in 2004 by Alcatel and Thales, the III-V Lab has enabled rapid development of a common platform for dual-use optoelectronic and microelectronic technology for markets addressed by the two groups, such as telecom, space, defense and security. CEA-Leti will significantly broaden the scope of the lab’s targeted applications by combining its IP and expertise in silicon, microelectronics and microsystems and in heterogeneous integration.

Focusing on practical applications for the combined potential of semiconductors and silicon, the III-V Lab will focus on four primary areas of research and markets:

  • Integrated photonic circuits that combine the active and passive functions of III-V and silicon for high-speed telecommunications and data transfer;
  • High-power and microwave GaN-based microelectronics to increase the power density, robustness, energy efficiency and compactness of telecommunication, avionics, satellite, defense, energy and transport systems;
  • A new generation of cost-effective, compact, ultra-sensitive, highly-selective gas sensors for use in security, industrial process control, and environmental monitoring; and
  • Thermal and near-infrared imagery for security and defense applications. The lab will develop new types of detectors with increased resolution while reducing overall cost and speeding their adoption in the industrial-quality control, transportation and environmental markets.

"The integration in a silicon microelectronic platform is on our roadmap to further improve performance, cost and energy consumption," said Gee Rittenhouse, head of Research at Alcatel-Lucent Bell Labs.

"As the third partner in the III-V lab, Leti adds deep expertise and essential silicon capabilities to our existing strengths in III-V semiconductors, opening broader opportunities for innovation. Thales will be provided stronger competitive advantages through the III-V Lab, thanks to the early availability for system developments of new components with breakthrough performances," said Marko Erman, SVP Research & Technology at Thales.

Leti CEO Laurent Malier added that the joint venture model enables partners to accomplish technologies and goals that were unacheivable in silos. "Moreover, each partner can capitalize on the developments and transfer new technologies to our customers."

III-V Lab is located south of Paris in what will become the heart of the Paris Sud Saclay project, a major science and technology park that will combine research organizations, universities, Grandes Ecoles and corporate facilities.

Alcatel-Lucent (Euronext Paris and NYSE : ALU) is a leader in mobile, fixed, IP and optics technologies, and a pioneer in applications and services. Alcatel-Lucent includes Bell Labs, one of the world’s foremost centres of research and innovation in communications technology. Learn more at http://www.alcatel-lucent.com

Thales is a global technology leader for the defense and security and aerospace and transport markets.

CEA is a French research and technology organization, with activities in four main areas: energy, information technologies, healthcare technologies and defense and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies in order to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications. For more information, visit www.leti.fr.

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March 4, 2011 — A little zinc can do a lot of damage to graphene. Rice University researchers have taken advantage of that to create single-atomic-layer lithography. The Rice lab of chemist James Tour sputtered zinc onto multilayered graphene, enabling the team to remove a single layer at a time without disturbing the layers beneath.

A microscopic checkerboard pattern shows the ability of Rice University’s new technique, as reported in Science, to remove single layers of graphene without disturbing the layers beneath. (Credit: Tour Lab/Rice University)

The discovery could be useful as researchers explore graphene’s electrical properties for new generations of microcircuitry and other graphene-based devices. Graphene, the one-atom-thick form of carbon, won its discoverers the most recent Nobel Prize in physics.

The researchers created a graphene checkerboard by removing horizontal and vertical layers to create a three-dimensional pattern. The researchers were able to create a 100nm line in a sheet of graphene, which suggests the only horizontal limit to the resolution of the process is the resolution of the metal patterning method.

"The next step will be to control the horizontal patterning with similar precision to what we have attained in the vertical dimension," Tour said. "Then there’s no more room at the bottom at any dimension, at least if we call single atoms our endpoint — which it is, for practical purposes."

"The removal of a single sheet of graphene or graphene oxide was a surprise," said Tour, Rice’s T.T. and W.F. Chao Chair in Chemistry as well as a professor of mechanical engineering and materials science and of computer science. "We thought multiple layers would be removed by this protocol, but to see single layers removed is one of those exciting events in science where nature gives us far more than we expected."

The Rice U. researchers printed a micro owl, Rice’s mascot, about 15 millionths of a meter wide. For the owl, Dimiev cut a stencil in PMMA with an electron beam and placed it on graphene oxide. He sputter-coated zinc through the stencil and then washed the zinc away with dilute hydrochloric acid, leaving the embedded owl behind. (Credit: Tour Lab/Rice University)

Tour said the ability to remove single layers of graphene in a controlled manner "affords the most precise level of device-patterning ever known, or ever to be known, where we have single-atom resolution in the vertical dimension. This will forever be the limit of vertical patterning — we have hit the bottom of the scale."

Ayrat Dimiev, a postdoctoral scientist in Tour’s lab, discovered the technique and figured out why graphene is so amenable to patterning. He sputtered zinc onto graphene oxide and other variants created through chemical conversion, chemical vapor deposition (CVD) and micromechanically (the "Scotch-tape" method). Bathing the graphene in dilute hydrochloric acid removed graphene wherever the zinc touched it, leaving the layers underneath intact. The graphene was then rinsed with water and dried in a stream of nitrogen.

Investigation of the sputtered surface before applying the acid wash revealed that the metals formed defects in the graphene, breaking bonds with the surrounding sheet like a cutter through chicken wire. Sputtering zinc, aluminum, gold and copper all produced similar effects, though zinc was best at delivering the desired patterning.

Sputter-coating graphene with aluminum showed similar effects. But when Dimiev tried applying zinc via thermal evaporation, the graphene stayed intact.

Results are reported this week in the journal Science. Read the abstract at: 

A team of Rice University researchers has developed a way to remove layers of graphene from a stack leaving underlying layers in a pristine state. Co-authors of a new Science paper on the research include, from left: Ayrat Dimiev, Alexander Slesarev, Professor James Tour, Zhengzong Sun and Alexander Sinitskii. Missing from the photo is former Rice postdoctoral researcher Dmitry Kosynkin. (Jeff Fitlow/Rice University)

http://www.sciencemag.org/content/331/6021/1168.abstract Co-authors include research associate Dmitry Kosynkin, postdoctoral research associate Alexander Sinitskii and graduate students Alexander Slesarev and Zhengzong Sun, all of Rice.

The Air Force Office of Scientific Research, the Air Force Research Lab through the University Technology Corporation, the Office of Naval Research Graphene MURI Program, and M-I SWACO funded the research.

Video of the researchers discussing their work is available at: http://www.youtube.com/watch?v=RqPg0rebSl8

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March 4, 2011 – A new global R&D consortium is seeking companies to join its efforts working on embedding thin-film passive components into packages using through-silicon vias (TSV), for use in smart mobile electronics and implantable bio-electronic systems.

The Global Industry R&D Consortium in Thin Film Passive Components (TPC), housed at the Georgia Tech Packaging Research Center (PRC), will focus on micro/nanoscale high-density, low-loss capacitors and inductors as surface thin film passives on silicon or glass, and digital and RF passives as thin-film integrated passive devices (IPD) with high permittivity and permeability dielectrics and noise isolation structures. These then can be added into the package, realizing system miniaturization with improved performance.

Areas of research include:

– High-density inductors: High permeability and low-loss magnetic core for higher volumetric and power efficiency
– High-density capacitors: Advanced high-surface area electrodes and conformal dielectrics
– Package integration of supercapacitors and thin film batteries
– TSV and trench capacitors: Advanced dielectrics with low-cost wafer-compatible processes.
– RF components: Stable dielectrics with high permittivity and permeability
– EMI isolation: Horizontal and vertical EMI isolation in 3D systems.

And the consortium’s listed goals:

– Power supply components with 10-100X enhancement in component volumetric efficiency;
– Enhanced film properties for lower loss and improved efficiency;
– Power integrity in high-speed processors and 3D ICs;
– Integrated energy storage in packages;
– Stable dielectrics with high permittivity and permeability at high frequencies;
– Tunable thin-film components;
– Noise isolation in mixed-signal systems

The PRC’s previous work led to high-density capacitors on silicon and organic packages to demonstrate power noise suppression in high-speed digital systems, and novel magnetic composites for high-density inductors. It also has led work developing and integrating high-Q RF components on silicon and organic packages, novel high permittivity and high permeability materials for miniaturizing RF components as well as unique EMI isolation structures.

More info about the TPC consortia, including contacts for companies interested in joining, are at http://www.prc.gatech.edu/partnership/TPC/.

Debra Vogler, senior technical editor

March 3, 2011 —  "You can’t approach the future by predictions. You approach the future by making it happen," Terry Brewer, founder/president of Brewer Science, says. And this mindset carries over into real-world results Click to Enlargefor the semiconductor industry, he points out: "EUV will happen if we want to make it happen."

SST’s Debra Vogler caught up with Terry Brewer at the SPIE Advanced Lithography symposium (Feb. 28 – March 3 in San Jose, CA). He reflects on the company’s 30 years in business, revisits the importance of "personal mastery" and having a vision — beyond simply having ideas, it’s condensing them into substance and driving toward an outcome.

Listen to Terry Brewer’s talk

Brewer Science also announced a series of products at SPIE Advanced Lithography, OptiStack and the ARC 300 coating series.

March 4, 2011 — Researchers in the University of Arizona’s physics department, along with collaborators from the Massachusetts Institute of Technology (MIT) and the National Materials Science Institute in Japan, found that by placing a graphene layer on a material almost identical in structure, boron nitride (BN), instead of the commonly used silicon oxide (SiO2) found in microchips, they could significantly improve its electronic properties.

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Placed on boron nitride, graphene shows much smaller electric charge fluctuations, shown in red and blue (left) than when mounted on a silicon oxide wafer (right). (Image courtesy of Brian LeRoy/UA)

The study of the physical properties and potential applications of graphene has suffered from a lack of suitable carrier materials that can support a flat graphene layer while not interfering with its electrical properties, the researchers said.

Substituting silicon wafers with boron nitride, a graphene-like structure consisting of boron and nitrogen atoms in place of the carbon atoms, the group was the first to measure the topography and electrical properties of the resulting smooth graphene layer with atomic resolution.

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Under the scanning tunneling microscope, graphene reveals its honeycomb structure made up of rings of carbon atom, visible as small hexagons. The larger hexagons result from an interference process occurring between the graphene and the underlying boron nitride. The scale bar measures one nanometer, or one billionth of a meter. (Image courtesy of Brian LeRoy/UA)

"Structurally, boron nitride is basically the same as graphene, but electronically, it’s completely different," said Brian LeRoy, an assistant professor of physics and senior author of the study. "Graphene is a conductor, boron nitride is an insulator."

"We want our graphene to sit on something insulating, because we are interested in studying the properties of the graphene alone. For example, if you want to measure its resistance, and you put it on metal, you’re just going to measure the resistance of the metal because it’s going to conduct better than the graphene."

To measure the topography of the graphene surface, the team uses a scanning tunneling microscope, which has an ultrafine tip that can be moved around. "We move the tip very close to the graphene, until electrons start tunneling to it," Jiamin Xue, a doctoral student in LeRoy’s lab and the paper’s leading author, explained. "That’s how we can see the surface. If there is a bump, the tip moves up a bit."

"Using a scanning tunneling microscope, we can look at atoms and study them," Leroy added. "When we put graphene on silicon oxide and look at the atoms, we see bumps that are about a nanometer in height. Boron nitride…smooths out the bumps by an order of magnitude."

For the spectroscopic measurement, Xue holds the tip at a fixed distance above the sample. He then changes the voltage and measures how much current flows as a function of that voltage and any given point across the sample. This allows him to map out different energy levels across the sample.

"You want as thin an insulator as possible," LeRoy added. "The initial idea was to pick something flat but insulating. Because boron nitride essentially has the same structure as graphene, you can peel it into layers in the same way. Therefore, we use a metal as a base, put a thin layer of boron nitride on it and then graphene on top."

"When you have graphene sitting on silicon oxide, there are trapped electric charges inside the silicon oxide in some places, and these induce some charge in the overlying graphene. You get quite a bit of variation in the density of electrons. If graphene sits on boron nitride, the variation is two orders of magnitude less," LeRoy said.

The team’s results are published in the advance online publication of Nature Materials.


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Jiamin Xue, Philippe Jacquod and Brian LeRoy (left to right) with the scanning tunneling microscope they use to study graphene. (Photo by Patrick McArdle/UANews)

In addition to potential applications in integrated circuits, solar cells, miniaturized bio devices and gas molecule sensors, graphene has attracted the attention of physicists for its unique properties in conducting electricity on an atomic level. Graphene has little resistance and allows electrons to behave as massless particles like photons while traveling through the hexagonal grid at very high speeds.

The UA portion of this research was funded by the U.S. Army Research Office and the National Science Foundation.

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March 4, 2011 — Gigaphoton released the latest developments in its EUV source program at this week’s SPIE Advanced Lithography conference. The company reported achieving a conversion efficiency (CE) of 3.3% with tin droplets <20µm in diameter (see figure) with its plasma-based laser produced plasma (LPP).

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Figure. Conversion efficiency vs. droplet size for tin plasma-based LPP EUV source. SOURCE: Gigaphoton

Click to EnlargeIn a podcast interview at the conference, Kenji Takahisa, manager in Gigaphoton’s management planning department, explained the physics behind the performance. Listen to the interview: Download (iPhone/iPod users) or Play Now

The key is the use of a short wavelength pre-pulse to irradiate the tin droplet. The small focus size of the pre-pulse laser penetrates the tin droplets, creating optimal conditions (i.e., an ideal "fine mist"). When the main laser irradiates the target droplet, a "perfect mist" is distributed in the focal plane of the CO2 main laser; the mist is transformed into vapor and is ionized. Any remaining debris, which is also ionized, can then be guided by a magnetic mitigation system to a tin "catcher" away from the collector mirror. Such mitigation ensures a longer life of the collector mirror. Takahisa also explains the experimental data shown in the figure in the interview.

More from SPIE Advanced Lithography 2011:

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By Debra Vogler, senior technical editor

March 3, 2011 — Nigel Farrar, VP, marketing & lithography technology, Cymer, provides an update on extreme ultra violet (EUV) source technology — including training and next-generation timelines — in a podcast interview at SPIE Advanced Lithography conference (2/27-3/3/11, San Jose, CA).

Click to EnlargeListen to Farrar’s interview: Download (iPhone/iPod users) or Play Now

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Figure 1. Lithography tool cost of ownership reduction. Cymer’s iGLX technology enables reduced cost of ownership by using 20% less fluorine mix over GLX and GLX2. SOURCE: Cymer.

Deep ultra-violet (DUV) lithography highlights include enhancements to Cymer’s ArF immersion laser, the XLR600ix. At SPIE, Cymer presented an update that further extends gas lifetime (Fig. 1). By doubling the gas life time, Cymer has enabled up to two months between gas refills (depending on the pulse usage).

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Process window for 1.35NA ArFi exposure for norminal light-source bandwidth (0.35pm E95) and a focus drilling spectrum (1.3pm E95)
Figure 2. Depth-of-focus (DOF) improvements with focus drilling technology. For this simulated structure with pitch of 165nm, a 60-70% DOF increase can be obtained using the Cymer Focus Drilling spectrum (at 1.3pm E95) over the nominal light-source operation (0.35pm E95) at best dose. SOURCE: Cymer.

Cymer also introduced focus drilling (Fig. 2), which uses a broad bandwidth for contact and via layers to enhance depth-of-focus.

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