Consumer demand for higher performance and lower power microchips is driving the need to continue scaling CMOS technology. Fabricating devices with low power consumption and good short channel device control becomes increasingly difficult with traditional methods (smaller dimensions). Continued scaling will require the introduction of both new materials and new device integration schemes. This article addresses how front end technologists are reacting to address these challenges.
Bill Taylor, Chris Hobbs, SEMATECH, Albany NY, USA
The maximum current obtained from the nominal transistor (Id) is an important criteria in determining chip performance (components shown in Fig. 1). Scaling the transistor size to increase the packing density involves decreasing both the width (W) and gate length (L). Although some improvement in the total drive current can be obtained by increasing the W/L ratio, the desire to use leading edge photolithography to aggressively produce small W and L dimensions to maximize the transistor density on a chip tends to keep the W/L ratio more or less constant, except in specific devices. This is why it’s important to find other knobs to increase performance.
Figure 1. Components of transistor drive current, and examples of how to improve it: a) Reducing parasitics to improve Vchan, and b), c) external and internal stressors to improve channel mobility. External stressors wrap around the device, whereas internal stressors are part of the device, such as using SiGe S/D junctions.
As device gate length shrinks, the source and drain get closer together. To prevent the increased risk of leakage/shorting, the driving voltage must also reduce. While this helps to keep power consumption low, it reduces the gate overdrive (Vg-Vt), and Vt cannot be significantly reduced. The voltage across the channel can be maximized by minimizing parasitic resistances, which can consume 0.2V or more. Reducing these parasitics is driving development in milli/micro-second (flash lamp, laser) anneals (improved activation and abruptness), new silicides, and new contacts (Cu vs W).
The mobility (µ), or speed of the electrons/holes is a crucial parameter that has spawned a range of approaches, including stressors, new materials, and new architectures. When silicon is strained, the mobility changes – electrons and holes move more freely in silicon under tensile/compressive (respectively) stresses applied to specific orientations allowing significant drive current improvements. External stressors are typically nitride layers wrapping over the device that biaxially squeeze/stretch the channel as desired. Internal stressors are typically epitaxially grown SiGe or SiC-based layers grown inside a hollowed-out source/drain region, acting uniaxially in the gate length direction. The Ge atom, being a larger atom than Si, results in a compressive squeeze on the channel (used on PMOS), while the small C atom in SiC-based epi results in a tensile strain (helpful on NMOS). These changes in mobility are also dependent upon alignment of the channel with different directions in the lattice (<110> vs <100>), leading chipmakers to consider non-standard wafers, or even integrations with both orientations .
Strain techniques have been employed for several generations, making up for lack of dielectric scaling as high-k/metal gate (HK+MG) was developed. Now, the dependence of mobility improvement on strain has become extremely important and current technologies obtain 40% or more of their drive current through strain enhancement. A significant issue with all of these strain approaches is that scaling reduces their effectiveness (for example, less ‘gripping area’ on which the external stressor can act).
To overcome this reduction in effectiveness of strain techniques on further scaled devices, one can move to a completely different channel material with an inherently higher mobility (Ge and III-V materials offer mobilities >3 to 10x of silicon). This, however, introduces significant challenges in materials selection, processing and integration, perhaps most significantly the interface between the high mobility channel and Si substrate, and selection of a suitable gate dielectric (some form of high-k) for the new channel material.
Drive current − and to some extent, mobility, and off-state control improvement − can also be accomplished via modifications to device architecture. If the area under the gate that transports carriers during inversion can be maximized without compromising the S-D distance, one can get better drive current overall in a device with good off-state current control. Extending the channel in the third dimension to form a "fin," and adding a second (or a third or multiple) gate(s), allows one to increase Id. Another major inhibitor of mobility is the extra dopant (halo) implanted at the edges of the junction extension regions to help leakage and obtain better gate control of the device. This extra dopant can be eliminated (and net device mobility improved) with a second gate. Furthermore, the control offered by the second gate enables one to eliminate doping in the channel, and thus improve device mobility. Figure 2 shows the evolution of a conventional planar device to a double gate FinFET.
Figure 2. a, b) The gate loses control of the channel as planar MOSFETs are scaled; c) A thin silicon channel with a gate on both sides helps maintain control of the channel; and d) Multigate devices are easier to fabricate with a vertical fin and wrap-around gate.
The last knob in the equation for drive current improvement is the gate capacitance (Cox), which is proportional to the ratio of dielectric constant k and thickness (k/t). As the gate length is reduced, to maintain electrical control of the channel region so that the gate can still switch the channel off and on, it’s important to bring the gate electrode closer to the channel region. This has been the motivation to aggressively scale the SiO2 gate dielectric thickness and use high-k to achieve low equivalent oxide thickness (EOT). Multi-gate devices such as FinFETs, omega-gate, and gate-all-around have an inherent advantage over conventional planar devices because the geometry enables better electrostatic control of the channel region . This is attractive from a transistor design perspective because the EOT of a multi-gate device can be relaxed 1-2 Angstroms and still provide similar short channel control as a planar device. EOT scaling on multi-gate devices is still needed as technology nodes change, but the transition from single to multi-gate architecture will provide an extension to the EOT window and a bit of relief from the immediate need for aggressive EOT scaling, and resultant leakage and reliability deterioration.
Circuits being designed today require devices with different threshold voltages (low, medium and high) to minimize power consumption. Conventional planar CMOS technologies use a combination of multiple gate dielectric thicknesses and implant tuning into the channel region to provide these multiple Vts. To take advantage of the lower mobility scattering offered by the undoped channel on multi-gate devices, it’s desirable to avoid implanting the channel. This implies that a non-planar device technology has an inherent advantage because the undoped channel allows low threshold voltages to be achieved and tuned easier with gate work functions further from the band edges.
With so many inherent advantages, 3D transistor devices are really a question of "when" not "if." However, given the dominance of strain as a performance enhancement option in today’s planar technologies, this makes it clear that strain engineering is critical to incorporate in FinFETs and gate-all-around devices. This needs careful study since unlike planar devices, multiple orientations of Si come into play in 3D devices. Stress along the wrong orientations can actually inhibit transport in a worst case scenario. Given the enhanced exposure of the channel area, one could contemplate increased opportunity to apply stresses. However, this increases integration complexity and a more systematic study of most effective/ineffective approaches is needed to unleash the potential of 3D devices.
This brief sweep across front end technology shows how strain and high-k/metal gates have been used to answer near-term scaling challenges. A consistent theme has been the introduction of new materials, and this will only expand in future nodes as strain techniques lose their effectiveness due to shrinking dimensions and technologists look to integrations more advanced than conventional planar FETs.
1. M. Yang, et al., "High Performance CMOS SOI Devices on Hybrid Crystal Oriented Substrates," IEDM 2003.
2. J. Kavalieros et al., "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering," Symposium on VLSI Technology 2006.
Bill Taylor is the electrical physical characterization program manager at SEMATECH, 257 Fuller Road Albany NY 12203 USA; ph.: 518-649-1000; email email@example.com.
Chris Hobbs is the non-planar CMOS project manager at SEMATECH.
Solid State Technology | Volume 54 | Issue 3 | March 2011